19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming

2014 ◽  
Author(s):  
Ki-Tae Park ◽  
Jin-man Han ◽  
Daehan Kim ◽  
Sangwan Nam ◽  
Kihwan Choi ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Speed ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory

Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming

2015 ◽  
Vol 50 (1) ◽  
pp. 204-213 ◽  
Author(s):  
Ki-Tae Park ◽  
Sangwan Nam ◽  
Daehan Kim ◽  
Pansuk Kwak ◽  
Doosub Lee ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Speed ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory

scholarly journals CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory

2021 ◽  
Vol 7 (3) ◽  
pp. eabe1341 ◽  
Author(s):  
Min-Kyu Kim ◽  
Ik-Jyae Kim ◽  
Jang-Sik Lee
Keyword(s):  
Flash Memory ◽  
Interfacial Layer ◽  
High Speed ◽  
Three Dimensional ◽  
Perovskite Oxides ◽  
Processing Temperature ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
3D Integration ◽  
Ferroelectric Memory

Ferroelectric memory has been substantially researched for several decades as its potential to obtain higher speed, lower power consumption, and longer endurance compared to conventional flash memory. Despite great deal of effort to develop ferroelectric memory based on perovskite oxides on Si, formation of unwanted interfacial layer substantially compromises the performance of the ferroelectric memory. Furthermore, three-dimensional (3D) integration has been unimaginable because of high processing temperature, non-CMOS compatibility, difficulty in scaling, and complex compositions of perovskite oxides. Here, we demonstrate a unique strategy to tackle critical issues by applying hafnia-based ferroelectrics and oxide semiconductors. Thus, it is possible to avoid the formation of interfacial layer that finally allows unprecedented Si-free 3D integration of ferroelectric memory. This strategy yields memory performance that could be achieved neither by the conventional flash memory nor by the previous perovskite ferroelectric memories. Device simulation confirms that this strategy can realize ultrahigh-density 3D memory integration.

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Array

Novel Concept of the Three-Dimensional Vertical FG nand Flash Memory Using the Separated-Sidewall Control Gate

2012 ◽  
Vol 59 (8) ◽  
pp. 2078-2084 ◽  
Author(s):  
Moon-Sik Seo ◽  
Bong-Hoon Lee ◽  
Sung-Kye Park ◽  
Tetsuo Endoh
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Novel Concept

Nanophotonic identification of defects buried in three-dimensional NAND flash memory devices

2018 ◽  
Vol 1 (1) ◽  
pp. 60-67 ◽  
Author(s):  
Jae Woong Yoon ◽  
Seong-Min Ma ◽  
Gun Pyo Kim ◽  
Yoonshik Kang ◽  
Joonseong Hahn ◽  
...  
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Memory Devices ◽  
Nand Flash ◽  
Nand Flash Memory

A Novel Bit-Flipping LDPC Decoder for Solid-State Data Storage

2014 ◽  
Vol 513-517 ◽  
pp. 2094-2098 ◽  
Author(s):  
Wen Zhe Zhao ◽  
Kai Zhao ◽  
Qiu Bo Chen ◽  
Min Jie Lv ◽  
Zuo Xun Hou
Keyword(s):  
Solid State ◽  
Error Correction ◽  
Data Storage ◽  
Flash Memory ◽  
Message Passing ◽  
High Speed ◽  
Design Solution ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
State Data

This paper concerns the design of high-speed and low-cost LDPC code bit-flipping decoder. Due to its inferior error correction strength, bit-flipping decoding received very little attention compared with message-passing decoding. Nevertheless, emerging flash-based solid-state data storage systems inherently favor a hybrid bit-flipping/message-passing decoding strategy, due to the significant dynamics and variation of NAND flash memory raw storage reliability. Therefore, for the first time highly efficient silicon implementation of bit-flipping decoder becomes a practically relevant topic. To address the drawbacks caused by the global search operation in conventional bit-flipping decoding, this paper presents a novel bit-flipping decoder design. Decoding simulations and ASIC design show that the proposed design solution can achieve upto 80% higher decoding throughput and meanwhile consume upto 50% less silicon cost, while maintaining almost the same decoding error correction strength.

Suppression of Inhibit Cell Vth Disturbance in Three Dimensional Stack NAND Flash Memory

2013 ◽  
Vol 13 (9) ◽  
pp. 6382-6388 ◽  
Author(s):  
Byeong-In Choe ◽  
Byung-Gook Park ◽  
Jung-Kyu Lee ◽  
Jong-Ho Lee
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory
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