A Novel Bit-Flipping LDPC Decoder for Solid-State Data Storage

2014 ◽  
Vol 513-517 ◽  
pp. 2094-2098 ◽  
Author(s):  
Wen Zhe Zhao ◽  
Kai Zhao ◽  
Qiu Bo Chen ◽  
Min Jie Lv ◽  
Zuo Xun Hou
Keyword(s):  
Solid State ◽  
Error Correction ◽  
Data Storage ◽  
Flash Memory ◽  
Message Passing ◽  
High Speed ◽  
Design Solution ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
State Data

This paper concerns the design of high-speed and low-cost LDPC code bit-flipping decoder. Due to its inferior error correction strength, bit-flipping decoding received very little attention compared with message-passing decoding. Nevertheless, emerging flash-based solid-state data storage systems inherently favor a hybrid bit-flipping/message-passing decoding strategy, due to the significant dynamics and variation of NAND flash memory raw storage reliability. Therefore, for the first time highly efficient silicon implementation of bit-flipping decoder becomes a practically relevant topic. To address the drawbacks caused by the global search operation in conventional bit-flipping decoding, this paper presents a novel bit-flipping decoder design. Decoding simulations and ASIC design show that the proposed design solution can achieve upto 80% higher decoding throughput and meanwhile consume upto 50% less silicon cost, while maintaining almost the same decoding error correction strength.

Design of a Small-Sized High-Speed Data Storage Module Based on FPGA

2014 ◽  
Vol 912-914 ◽  
pp. 1556-1560
Author(s):  
Sheng Kun Li ◽  
Cheng Qun Chu ◽  
Hai Liang Chen ◽  
Fang Ma
Keyword(s):  
Data Storage ◽  
Flash Memory ◽  
High Speed ◽  
High Performance ◽  
Data Access ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Storage Unit ◽  
Field Programmable ◽  
High Speed Data

The large-capacity, high-speed and low power consumption become the new requirements for the data storage systems. In this paper, a high-performance storage module based on multiple NAND flash memory chips is presented to real-time massive data acquisition system. In order to achieve the miniaturization dimension and the high-speed data storage design requirements, the paper presents a small size and high-speed storage unit based on NAND flash, where the dimensions of the module can reach 33mm×33mm and the maximum rate is up to 60MB/s. Ensuring continuous and reliable operation requires a dedicated buffering for the data transmission. We analyze the elements and peculiarities of the flash memory chip and propose a multi-way architecture to speed up data access. The design of a multilevel high-speed buffer structure based on the field programmable gate array (FPGA) technology is introduced in the paper. The proposed system can be applicable to some portable digital equipment.

scholarly journals Highly reliable, high speed and low power NAND flash memory-based Solid State Drives (SSDs)

2012 ◽  
Vol 9 (8) ◽  
pp. 779-794 ◽  
Author(s):  
Ken Takeuchi ◽  
Teruyoshi Hatanaka ◽  
Shuhei Tanakamaru
Keyword(s):  
Solid State ◽  
Low Power ◽  
Flash Memory ◽  
High Speed ◽  
Nand Flash ◽  
Solid State Drives ◽  
Nand Flash Memory

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

scholarly journals ZDC: A Zone Data Compression Method for Solid State Drive Based Flash Memory

Symmetry ◽  
2020 ◽  
Vol 12 (4) ◽  
pp. 623
Author(s):  
Xin Ye ◽  
Zhengjun Zhai ◽  
Xiaochang Li
Keyword(s):  
Solid State ◽  
Data Compression ◽  
Data Storage ◽  
Flash Memory ◽  
Research Result ◽  
Nand Flash ◽  
Data Deduplication ◽  
Solid State Drive ◽  
Research Results ◽  
Hot Zone

Solid-state drive (SSD) with flash memory as the storage medium are being widely used in various data storage systems. SSD data compression means that data is compressed before it is written to Not-And (NAND) Flash. Data compression can reduce the amount of data written in NAND Flash and improve the performance and reliability of SSDs. At present, the main problem facing data compression of SSD is how to improve the efficiency of data compression and decompression. In order to improve the performance of data compression and decompression, this study proposes a method of SSD data deduplication based on zone division. First, this study divides the storage space of the SSD into zones and divides them into one hot zone and multiple cold zones according to the different erasing frequency. Second, the data in each zone is divided into hot data and cold data according to the number of erasures. At the same time, the address mapping table in the hot zone is loaded into the cache. Finally, when there is a write or read request, the SSD will selectively compress or decompress the data according to the type of different zones. Through simulation tests, the correctness and effectiveness of this study are verified. The research results show that the data compression rate of this research result can reach 70–95%. Compared with SSD without data compression, write amplification is reduced by 5 to 30%, and write latency is reduced by 5 to 25%. The research results have certain reference value for improving the performance and reliability of SSD.

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