Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application

Author(s):  
M. Chanda ◽  
A. S. Chakraborty ◽  
S. Nag ◽  
R. Modak
2017 ◽  
Vol 13 (3) ◽  
pp. 472-481 ◽  
Author(s):  
Manash Chanda ◽  
Tanushree Ganguli ◽  
Sandipta Mal ◽  
Anindita Podder ◽  
Chandan Kumar Sarkar

2015 ◽  
Vol 24 (10) ◽  
pp. 1550160 ◽  
Author(s):  
Manash Chanda ◽  
Swapnadip De ◽  
Chandan Kumar Sarkar

This paper shows that a conventional semi-custom design-flow based on a energy efficient adiabatic logic (EEAL) cell library allows any VLSI designer to design and verify complex adiabatic arithmetic units in a simple way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom EEAL-based 32-bit carry-lookahead adder (CLA) has been designed in a TSMC 90-nm CMOS process technology and verified by CADENCE Design suite. Differential cascode voltage swing (DCVS) logic has been used to implement the newly proposed EEAL and it uses only a sinusoidal clock supply to ensure correct operation. Post-layout simulations show that semi-custom adiabatic arithmetic units can save significant amount of energy, as compared to the previously reported single clocked adiabatic logic and logically equivalent static CMOS implementation. Extensive CADENCE simulations have been done for the verification of the functionality of the proposed logic structure.


Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 223 ◽  
Author(s):  
Yannan Zhang ◽  
Ke Han ◽  
and Jiawei Li

Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.


2013 ◽  
Vol 100 (6) ◽  
pp. 803-817 ◽  
Author(s):  
D. Nirmal ◽  
P. Vijayakumar ◽  
P. Patrick Chella Samuel ◽  
Binola K. Jebalin ◽  
N. Mohankumar

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