Leakage Power Reduction in 32-bit Digital Comparator Using Modified Power Gating Technique

2015 ◽  
Vol 742 ◽  
pp. 741-744 ◽  
Author(s):  
G. Amuthavalli ◽  
R. Gunasundari ◽  
A. Nijandan
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Channel Length ◽  
Power Reduction ◽  
Leakage Power ◽  
Power Gating ◽  
Dynamic Power ◽  
Digital Comparator ◽  
Static Power ◽  
Scaling Down

As scaling down of CMOS transistor’s channel length is done for miniaturization, the design community primarily focuses on the high performance & power-aware design. The power consumption of any circuit solely holds the performance and the life of it. But static power consumption deteriorates them and dominates the dynamic power consumption because of its leakage components. A modified approach of pulse triggering in the Power Gating technique called MPG (Modified Power Gating) is proposed to reduce the static power consumption (leakage power) of digital subsystems. Sub threshold leakage power of MPG Inverter (INV) and 32-bit Digital Comparator (DC) is analyzed and reduced with 35% to 40% leakage savings compared with conventional and existing techniques by simulating it in Cadence GPDK.

Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating

2016 ◽  
Vol 26 (03) ◽  
pp. 1750041 ◽  
Author(s):  
Abhishek Nag ◽  
Debanjali Nath ◽  
Sambhu Nath Pradhan
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Power Gating ◽  
Dynamic Power ◽  
Low Area ◽  
Average Area ◽  
Manual Intervention ◽  
Look Up Table ◽  
Area Overhead ◽  
Field Programmable

Leakage power reduction of an SRAM-based look-up table (LUT) in field-programmable gate array (FPGA) has been achieved in this work by implementing an efficient and dynamic power gating technique. The logic of gating is based on the theory of automatically shutting down the power supply to the inactive blocks of LUT during runtime, contrary to all previous works which involved manual intervention for the implementation of power gating. Two techniques of power gating are introduced in this work, PG1 and PG2. PG1 results in more power savings than PG2, however, PG2 has an advantage of low area overhead. Simulation has been carried out for all possible input combinations of LUT, designed in Cadence Virtuoso tool at 45[Formula: see text]nm technology. The results indicate a leakage power reduction of up to 50% in PG1 technique, with an average area overhead of 14.15%. The power savings in PG2 is up to 38%, with a minimal increase in area of 1.76%. The power bounce noise is also analyzed for the proposed techniques and reported.

Design for Test and Diagnosis of Power Switches

2015 ◽  
Vol 25 (03) ◽  
pp. 1640013
Author(s):  
Miroslav Valka ◽  
Alberto Bosio ◽  
Luigi Dilillo ◽  
Patrick Girard ◽  
Arnaud Virazel ◽  
...  
Keyword(s):  
Power Consumption ◽  
Industrial Test ◽  
Design For Test ◽  
Power Gating ◽  
Test Quality ◽  
Worst Case ◽  
Manufacturing Defects ◽  
Efficient Test ◽  
Power Switches ◽  
Static Power

Power gating techniques have been adopted so far to reduce the static power consumption of integrated circuits (ICs). Power gating is usually implemented by means of several power switches (PSs). Manufacturing defects affecting PSs can lead to increase in the actual static power consumption and, in the worst case, they can completely isolate a functional block in the IC. Thus, efficient test and diagnosis solutions are needed. In this paper, we present a novel Design for Test and Diagnosis (DfTD) solution able to increase the test quality and diagnosis accuracy of PSs. The proposed approach has been validated through SPICE simulations on ITC’99 benchmark circuits as well as on industrial test cases.

scholarly journals An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

2017 ◽  
Vol 6 (02) ◽  
pp. 07-12
Author(s):  
Diksha Siddhamshittiwar
Keyword(s):  
Average Power ◽  
Full Adder ◽  
Deep Submicron ◽  
Power Reduction ◽  
Vlsi Circuits ◽  
Power Gating ◽  
Static Power ◽  
Simulation Results ◽  
Efficient Power ◽  
Standby Mode

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

scholarly journals ROBUST AND SECURE S-BOX DESIGN WITH GATED HYBRID ENERGY RECOVERY LOGIC (GHERL) FOR IOT APPLICATIONS

10.6036/10108 ◽  
2022 ◽  
Vol 97 (1) ◽  
pp. 79-84
Author(s):  
RUBAN GLADWIN ◽  
NEHRU KASTHURI
Keyword(s):  
Internet Of Things ◽  
Power Consumption ◽  
Cyber Security ◽  
Energy Recovery ◽  
High Energy ◽  
Leakage Power ◽  
Handheld Devices ◽  
Power Gating ◽  
Hybrid Energy ◽  
Adiabatic Logic

The smart Internet of Things (IoT) network relies heavily on data transmission over wireless channels. Hence, it should be designed to be robust against the attacks from hackers and antagonists. The confidentiality in IoT devices is directly proportional to the complexity and power consumption. To mitigate these issues, this paper proposes a secure Substitution Box (S-Box) design that is exploited in the IoT for cyber security applications. The S-Box is based on Gated Hybrid Energy Recovery Logic (GHERL) that is an amalgamation of two different techniques as adiabatic logic and power gating. Adiabatic logic is preferred to attain high energy efficiency in practical applications such as portable and handheld devices. Power gating technique is preferred to reduce the leakage power and energy consumption. The proposed GHERL XOR gate and S-Box are implemented with 125nm technology in Tanner EDA tool. The consequences of the experiments exhibits that the novel S-Box design with GHERL XOR decreases the power consumption by 1.76%, 35.26%, 36.81%, 41.01% and reduces the leakage power by 58.54%, 20.27%, 27.38%, 13.63% when compared with the existing techniques such as S-Box with sleep transistor, dual sleep transistor, dual-stack and sleepy keeper approach. Keywords: Adiabatic logic, Power Gating, Internet of Things, S-Box

scholarly journals Low Power Checks in Multi Voltage Designs

2020 ◽  
Vol 11 ◽  
pp. 105-111
Author(s):  
K. R. Haripriya ◽  
Ajay Somkuwar ◽  
Laxmi Kumre
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Semiconductor Industry ◽  
Power Saving ◽  
Critical Issue ◽  
Leakage Power ◽  
Design Flow ◽  
Power Gating ◽  
Low Power Architectures

Leakage power consumption has been almost a serious problem these days in semiconductor industry. Many low power techniques like multi-voltage, power gating etc. are deployed to improve power saving. Power aware verification hence has become a critical issue now. Static low power verification has been developed to verify that low power architectures are designed in correct approach meeting all electrical rules in SoC. The UPF(Unified Power Format) is the standardized format that has all power intent information and can be used throughout the design flow to ensure that the power specification is intact. Firstly, this paper describes the special cells and its operation used in low power techniques. Secondly it describes the major checks examined at each stage using Synopsys VCLP tool and finally debugging with the tool and conclusion.

scholarly journals SIGNAL-PATH-LEVEL DUAL-Vt ASSIGNMENT FOR LEAKAGE POWER REDUCTION

2006 ◽  
Vol 15 (02) ◽  
pp. 197-216 ◽  
Author(s):  
YU WANG ◽  
HUAZHONG YANG ◽  
HUI WANG
Keyword(s):  
Threshold Voltage ◽  
High Performance ◽  
Low Voltage ◽  
Power Reduction ◽  
Threshold Voltages ◽  
Fast Development ◽  
Static Power ◽  
Signal Path ◽  
Subcircuit Extraction ◽  
New Algorithms

Along with the fast development of dual-threshold voltage (dual-Vt) and multi-threshold technology, it is possible to use them to reduce static power in low-voltage high-performance circuits. In this paper, we propose a new method to realize CMOS digital circuits that are implemented with dual-Vt technology. We first present a new signal-path-level circuit model which effectively deals with the fact that there can be two threshold voltages assigned to a single gate. In order to assign proper threshold voltage to all the signal-paths in the circuit, our new algorithms introduce the concept of subcircuit extraction and include the hierarchy algorithms which are effective and fast. Experimental results show that our algorithms produce a significant reduction for the ISCAS85 benchmark circuits.

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