Optimal timing for skew-tolerant high-speed domino logic

2003 ◽  
Author(s):  
Seong-Ook Jung ◽  
Ki-Wook Kim ◽  
Sung-Mo Kang
Keyword(s):  
High Speed ◽  
Optimal Timing ◽  
Domino Logic

High-Speed Digital Domino Logic for Ultra-Low Supply Voltages

2017 ◽  
Vol 36 (12) ◽  
pp. 4774-4788
Author(s):  
Omid Mirmotahari ◽  
Yngvar Berg
Keyword(s):  
High Speed ◽  
Domino Logic ◽  
Supply Voltages

Design of Low Power and High Speed VLSI Domino Logic Circuit

2018 ◽  
Author(s):  
Praveen J ◽  
Aishwarya Aishwarya ◽  
Jagadish Venkatraman Naik ◽  
Kshithija Kshithija ◽  
Mahesh Biradar
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Circuit ◽  
Domino Logic

A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic

2008 ◽  
Vol 16 (5) ◽  
pp. 594-598 ◽  
Author(s):  
Chua-Chin Wang ◽  
Chi-Chun Huang ◽  
Ching-Li Lee ◽  
Tsai-Wen Cheng
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
High Speed ◽  
Domino Logic ◽  
Dual Threshold Voltage

A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology

2019 ◽  
Vol 28 (10) ◽  
pp. 1950165 ◽  
Author(s):  
Sandeep Garg ◽  
Tarun K. Gupta
Keyword(s):  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Power Reduction ◽  
Maximum Power ◽  
Oxide Semiconductor ◽  
Domino Logic ◽  
Maximum Delay

In this paper, a fin field-effect transistor (FinFET)-based domino technique dynamic node-driven feedback transistor domino logic (DNDFTDL) is designed for low-power, high-speed and improved noise performance. In the proposed domino technique, the concept of current division is explored below the evaluation network for enhancement of performance parameters. Simulations are carried out for 32-nm complementary metal–oxide–semiconductor (CMOS) and FinFET node using HSPICE for 2-, 4-, 8- and 16-input OR gates with a DC supply voltage of 0.9[Formula: see text]V. Proposed technique shows a maximum power reduction of 73.93% in FinFET short-gate (SG) mode as compared to conditional stacked keeper domino logic (CSKDL) technique and a maximum power reduction of 72.12% as compared to modified high-speed clocked delay domino logic (M-HSCD) technique in FinFET low-power (LP) mode. The proposed technique shows a maximum delay reduction of 35.52% as compared to voltage comparison domino (VCD) technique in SG mode and a reduction of 25.01% as compared to current mirror footed domino logic (CMFD) technique in LP mode. The unity noise gain (UNG) of the proposed circuit is 1.72–[Formula: see text] higher compared to different existing techniques in FinFET SG mode and is 1.42–[Formula: see text] higher in FinFET LP mode. The Figure of Merit (FOM) of the proposed circuit is up to [Formula: see text] higher as compared to existing domino logic techniques because of lower values of power, delay and area and higher values of UNG of the proposed circuit. In addition, the proposed technique shows a maximum power reduction of up to 68.64% in FinFET technology as compared to its counterpart in CMOS technology.

Improved Domino logic for high speed design

2003 ◽  
Vol 39 (8) ◽  
pp. 644 ◽  
Author(s):  
Song Jia ◽  
Fei Liu ◽  
Lijiu Ji
Keyword(s):  
High Speed ◽  
Domino Logic ◽  
High Speed Design

High-speed low-power FinFET based domino logic

2009 ◽  
Author(s):  
Seid Hadi Rasouli ◽  
Hanpei Koike ◽  
Kaustav Banerjee
Keyword(s):  
Low Power ◽  
High Speed ◽  
Domino Logic

scholarly journals High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

ETRI Journal ◽  
2019 ◽  
Vol 41 (3) ◽  
pp. 383-395 ◽  
Author(s):  
A. Anita Angeline ◽  
V. S. Kanchana Bhaaskaran
Keyword(s):  
High Speed ◽  
Logic Circuits ◽  
Domino Logic
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