Silent Sharing: An Efficient Mechanism to Fast Sequential Program Execution on Chip Multicore Processor

2009 ◽  
Author(s):  
Liqiang He ◽  
Yan Sun
Keyword(s):  
Program Execution ◽  
Multicore Processor ◽  
Efficient Mechanism ◽  
Sequential Program ◽  
On Chip

scholarly journals Hardware-Assisted Security Monitoring Unit for Real-Time Ensuring Secure Instruction Execution and Data Processing in Embedded Systems

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1450
Author(s):  
Xiang Wang ◽  
Zhun Zhang ◽  
Qiang Hao ◽  
Dongdong Xu ◽  
Jiqing Wang ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Data Processing ◽  
Embedded System ◽  
High Performance ◽  
Program Execution ◽  
Security Monitoring ◽  
Railway Systems ◽  
On Chip ◽  
Capability Evaluation ◽  
Security Capability

The hardware security of embedded systems is raising more and more concerns in numerous safety-critical applications, such as in the automotive, aerospace, avionic, and railway systems. Embedded systems are gaining popularity in these safety-sensitive sectors with high performance, low power, and great reliability, which are ideal control platforms for executing instruction operation and data processing. However, modern embedded systems are still exposing many potential hardware vulnerabilities to malicious attacks, including software-level and hardware-level attacks; these can cause program execution failure and confidential data leakage. For this reason, this paper presents a novel embedded system by integrating a hardware-assisted security monitoring unit (SMU), for achieving a reinforced system-on-chip (SoC) on ensuring program execution and data processing security. This architecture design was implemented and evaluated on a Xilinx Virtex-5 FPGA development board. Based on the evaluation of the SMU hardware implementation in terms of performance overhead, security capability, and resource consumption, the experimental results indicate that the SMU does not lead to a significant speed degradation to processor while executing different benchmarks, and its average performance overhead reduces to 2.18% on typical 8-KB I/D-Caches. Security capability evaluation confirms the monitoring effectiveness of SMU against both instruction and data tampering attacks. Meanwhile, the SoC satisfies a good balance between high-security and resource overhead.

Designing of High Performance Multicore Processor with Improved Cache Configuration and Interconnect

2016 ◽  
pp. 204-219
Author(s):  
Ram Prasad Mohanty ◽  
Ashok Kumar Turuk ◽  
Bibhudatta Sahoo
Keyword(s):  
High Performance ◽  
Multicore Processors ◽  
Multicore Processor ◽  
Cache Size ◽  
L2 Cache ◽  
Internal Network ◽  
On Chip ◽  
L1 And L2 ◽  
The Impact ◽  
Cache Configuration

The growing number of cores increases the demand for a powerful memory subsystem which leads to enhancement in the size of caches in multicore processors. Caches are responsible for giving processing elements a faster, higher bandwidth local memory to work with. In this chapter, an attempt has been made to analyze the impact of cache size on performance of Multi-core processors by varying L1 and L2 cache size on the multicore processor with internal network (MPIN) referenced from NIAGRA architecture. As the number of core's increases, traditional on-chip interconnects like bus and crossbar proves to be low in efficiency as well as suffer from poor scalability. In order to overcome the scalability and efficiency issues in these conventional interconnect, ring based design has been proposed. The effect of interconnect on the performance of multicore processors has been analyzed and a novel scalable on-chip interconnection mechanism (INOC) for multicore processors has been proposed. The benchmark results are presented by using a full system simulator. Results show that, using the proposed INoC, compared with the MPIN; the execution time are significantly reduced.

Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies

2013 ◽  
Vol 135 (2) ◽  
Author(s):  
Wataru Nakayama
Keyword(s):  
Hot Spots ◽  
High Performance ◽  
Thermal Environment ◽  
Hot Spot ◽  
Air Cooling ◽  
Multicore Processor ◽  
Temperature Contrast ◽  
On Chip ◽  
Heat Spreading ◽  
Level Analysis

The objective of this study is to understand the effects of various parameters involved in the chip design and cooling on the occurrence of hot spots on a multicore processor chip. The thermal environment for the die is determined by the cooling design which differs distinctly between different classes of electronic equipment. In the present study, like many other hot spot studies, the effective heat transfer coefficient represents the thermal environment for the die, but, its representative values are derived for different cooling schemes in order to examine in what classes of electronic equipment the hot spot concern grows. The cooling modes under study are high-performance air-cooling, high-performance liquid-cooling, conventional air-cooling, and oil-cooling in infrared radiation (IR) thermography setup. Temperature calculations were performed on a model which is designed to facilitate the study of several questions that have not been fully addressed in the existing literature. These questions are concerned with the granularity of power and temperature distributions, thermal interactions between circuits on the die, the roles of on-chip wiring layer and the buried dioxide in heat spreading, and the mechanism of producing temperature contrast across the die. The main results of calculations are the temperature of the target spot and the temperature contrast across the die. Temperature contrasts are predicted in a range 10–25 K, and the results indicate that a major part of the temperature contrast is formed at a granularity corresponding to the size of functional units on actual microprocessor chips. At a fine granularity level and under a scenario of high power concentration, the on-chip wiring layer and the buried oxide play some roles in heat spreading, but their impact on the temperature is generally small. However, the details of circuits need to be taken into account in future studies in order to investigate the possibility of nanometer-scale hot spots. Attention is also called to the need to understand the effect of temperature nonuniformity on the processor performance for which low temperature at inactive cells makes a major contribution. In contrast to the situation for the die under forced convection cooling, the die in passively cooled compact equipment is in distinctly different thermal environment. Strong thermal coupling between the die and the system structure necessitates the integration of package and system level analysis with the die-level analysis.

scholarly journals On-Chip Debug Architecture for Multicore Processor

ETRI Journal ◽  
2012 ◽  
Vol 34 (1) ◽  
pp. 44-54 ◽  
Author(s):  
Hyeongbae Park ◽  
Jing-Zhe Xu ◽  
Kil Hyun Kim ◽  
Ju Sung Park
Keyword(s):  
Multicore Processor ◽  
On Chip

An Embedded Multicore Platform Exploration in Video Application Utilizing FPGA

2012 ◽  
Vol 505 ◽  
pp. 329-337
Author(s):  
Chun Hua Xiao ◽  
Zhang Qin Huang ◽  
Da Li
Keyword(s):  
High Performance ◽  
New Technology ◽  
Practical Significance ◽  
Single Chip ◽  
Multicore Processor ◽  
Design Problems ◽  
Video Application ◽  
Multiple Cores ◽  
Field Programmable ◽  
On Chip

Multi-processor is not a new technology, but with the development of modern silicon technology, it is possible to integrate multiple cores in a single chip package, which is called multicore processor. Whether in the desktop personal machine, or embedded applications, multicore processor has been a general trend, due to the requirement of high performance and design problems in single-core processor. Surrounded multi-screen provides a better sense of reality, which is widely used in the surveillance, military, exhibitions, and so on. With the advantages in parallel processing, multicore technology has an important practical significance and a broad prospect in these applications. In this paper, an exploration on multicore architecture is mainly focused on, from the perspectives of processing elements, memory hierarchy, and on-chip interconnection. A basic platform for multi-screen display is implemented on the Xilinx field programmable gate array (FPGA), and it illustrates that there is a 3.6 times higher performance than the corresponding single-core design, which provides a helpful guidance and revelation to further researches.

scholarly journals Thai Voice-Controlled Analysis for Car Parking Assistance in System-on-Chip Architecture

2020 ◽  
Author(s):  
Sethakarn Prongnuch ◽  
Suchada Sitjongsataporn
Keyword(s):  
English Word ◽  
System On Chip ◽  
Female Voice ◽  
Multicore Processor ◽  
Voice Command ◽  
Command Signals ◽  
Thai English ◽  
On Chip ◽  
Sd Card ◽  
Mel Frequency Cepstral Coefficient

This paper introduces an analysis of Thai speech recognition for controlled car parking assist in the system-on-chip architecture. The objective is to investigate the male and female voice command signals, including Thai and English words, issued by the native Thai users. Hardware and software co-design by the Xilinx VIVADO are designed on an ARM multicore processor and a reconfigurable system on a ZYBO board. The experiments for Thai and English word recognition are conducted by using the Mel-frequency cepstral coefficient approach and presented in the form of spectrograms. The comparison of a voice command via Bluetooth and a reference command stored on an SD card and the ZYBO embedded board on a miniature electric vehicle is verified with the Pearson’s correlation coefficient (PCC). The experimental results show the accuracies of the received Thai/English, male/female, and indoor/outdoor voice commands as compared with the reference voice commands in the noisy surroundings. Hence, our system can support Thai/English and male/female voice commands to perform a set of actions for maneuvering a car by the PCC.

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