Ferroelectric (Fe)-NAND Flash Memory With Batch Write Algorithm and Smart Data Store to the Nonvolatile Page Buffer for Data Center Application High-Speed and Highly Reliable Enterprise Solid-State Drives

2010 ◽  
Vol 45 (10) ◽  
pp. 2156-2164 ◽  
Author(s):  
Teruyoshi Hatanaka ◽  
Ryoji Yajima ◽  
Takeshi Horiuchi ◽  
Shouyu Wang ◽  
Xizhen Zhang ◽  
...  
Keyword(s):  
Solid State ◽  
Flash Memory ◽  
Data Center ◽  
High Speed ◽  
Nand Flash ◽  
Solid State Drives ◽  
Nand Flash Memory ◽  
Data Store ◽  
Smart Data

scholarly journals Highly reliable, high speed and low power NAND flash memory-based Solid State Drives (SSDs)

2012 ◽  
Vol 9 (8) ◽  
pp. 779-794 ◽  
Author(s):  
Ken Takeuchi ◽  
Teruyoshi Hatanaka ◽  
Shuhei Tanakamaru
Keyword(s):  
Solid State ◽  
Low Power ◽  
Flash Memory ◽  
High Speed ◽  
Nand Flash ◽  
Solid State Drives ◽  
Nand Flash Memory

A Novel Bit-Flipping LDPC Decoder for Solid-State Data Storage

2014 ◽  
Vol 513-517 ◽  
pp. 2094-2098 ◽  
Author(s):  
Wen Zhe Zhao ◽  
Kai Zhao ◽  
Qiu Bo Chen ◽  
Min Jie Lv ◽  
Zuo Xun Hou
Keyword(s):  
Solid State ◽  
Error Correction ◽  
Data Storage ◽  
Flash Memory ◽  
Message Passing ◽  
High Speed ◽  
Design Solution ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
State Data

This paper concerns the design of high-speed and low-cost LDPC code bit-flipping decoder. Due to its inferior error correction strength, bit-flipping decoding received very little attention compared with message-passing decoding. Nevertheless, emerging flash-based solid-state data storage systems inherently favor a hybrid bit-flipping/message-passing decoding strategy, due to the significant dynamics and variation of NAND flash memory raw storage reliability. Therefore, for the first time highly efficient silicon implementation of bit-flipping decoder becomes a practically relevant topic. To address the drawbacks caused by the global search operation in conventional bit-flipping decoding, this paper presents a novel bit-flipping decoder design. Decoding simulations and ASIC design show that the proposed design solution can achieve upto 80% higher decoding throughput and meanwhile consume upto 50% less silicon cost, while maintaining almost the same decoding error correction strength.

Reliability of Solid-State Drives Based on NAND Flash Memory

2017 ◽  
Vol 105 (9) ◽  
pp. 1725-1750 ◽  
Author(s):  
Neal R. Mielke ◽  
Robert E. Frickey ◽  
Ivan Kalastirsky ◽  
Minyan Quan ◽  
Dmitry Ustinov ◽  
...  
Keyword(s):  
Solid State ◽  
Flash Memory ◽  
Nand Flash ◽  
Solid State Drives ◽  
Nand Flash Memory
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