New Bi-Mode Gate-Commutated Thyristor Design Concept for High-Current Controllability and Low ON-State Voltage Drop

Carboxymethyl cellulose (CMC)-polyvinyl alcohol (PVA) and chitosan (CS)-polyvinyl alcohol were cross-linked by Fe3+and glutaraldehyde respectively to prepare cation exchange layer and anion exchange layer, and polyvinyl alcohol-sodium alginate (SA)-metal octocarboxyphthalocyanine (MePc (COOH)8, a kind of water splitting catalyst, here, Me stands for Fe3+or Co2+) nanofibers were prepared by electrospinning technique and introduced into the interlayer to obtain the CMC-PVA/PVA-SA-MePc (COOH)8/CS-PVA bipolar membrane (BPM). The experimental results showed that compared with the BPM without the PVA-SA-MePc (COOH)8interlayer, the water splitting efficiency at the interlayer of the CMC-PVA/PVA-SA-MePc (COOH)8/ CS-PVA BPM was obviously increased, and its membrane impedance decreased. When the concentration of FePc (COOH)8in the PVA-SA-FePc (COOH)8nanofibers was 3.0%, the trans-membrane voltage drop (IRdrop) of the CMC-PVA/PVA-SA-FePc (COOH)8/CS-PVA BPM was as low as 0.6V at a high current density of 90 mA/cm2.

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An AlGaAs/GaAs hetero source bipolar mode static induction transistor (HBSIT) with low forward voltage drop and high current gain

Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics ◽

10.1109/ispsd.1994.583759 ◽

2002 ◽

Author(s):

K. Nonaka ◽

Y. Ishikawa ◽

S. Yokoyama ◽

M. Abe ◽

T. Kamiyama

Keyword(s):

Voltage Drop ◽

Current Gain ◽

High Current ◽

Forward Voltage ◽

Bipolar Mode ◽

Forward Voltage Drop ◽

Static Induction Transistor ◽

Static Induction

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Forward voltage drop across a PN junction diode at high current densities †

International Journal of Electronics ◽

10.1080/00207217108938263 ◽

1971 ◽

Vol 31 (6) ◽

pp. 649-659

Author(s):

A. BAR-LEV

Keyword(s):

Voltage Drop ◽

High Current ◽

Forward Voltage ◽

Pn Junction ◽

Forward Voltage Drop ◽

Current Densities ◽

Junction Diode

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BURNING MODES OF A BIPOLAR PULSED DISCHARGE IN CO2

10.46813/2020-130-159 ◽

2020 ◽

pp. 159-164

Author(s):

V.A. Lisovskiy ◽

S.V. Dudin ◽

M.M. Vusyk ◽

V.D. Yegorenkov

Keyword(s):

Duty Cycle ◽

Voltage Drop ◽

Current Mode ◽

High Current ◽

Pulsed Discharge ◽

Frequency Range ◽

High Duty Cycle ◽

Cycle Amplitude ◽

Self Bias ◽

Voltage Axis

We have studied the burning modes of the bipolar pulsed discharge in CO2 within the frequency range between 20 and 300 kHz and the duty cycle of 11...97 %. The current and voltage waveforms within the pressure range between 0.1 to 1 Torr were registered. We have established that the duty cycle values may affect the axial structure of the discharge considerably causing the voltage drop redistribution across the electrodes. The bipolar pulsed discharge may burn in a high-current mode (with cathode sheaths near every electrode) as well as in a low-current one (with a low discharge current and weak glow). The transition between these modes may be observed at high duty cycle values. We have found that one may make a shift of the complete oscilloscope voltage pattern higher or lower along the voltage axis and produce a self-bias constant voltage the value and sign of which depend on the duty cycle, amplitude and frequency of the applied voltage.

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13-kV, 20-A 4H-SiC PiN Diodes for Power System Applications

Materials Science Forum ◽

10.4028/www.scientific.net/msf.778-780.855 ◽

2014 ◽

Vol 778-780 ◽

pp. 855-858 ◽

Cited By ~ 4

Author(s):

Dai Okamoto ◽

Yasunori Tanaka ◽

Tomonori Mizushima ◽

Mitsuru Yoshikawa ◽

Hiroyuki Fujisawa ◽

...

Keyword(s):

Power System ◽

High Voltage ◽

Light Emission ◽

Voltage Drop ◽

High Current ◽

Forward Voltage ◽

Pin Diodes ◽

Current Switching ◽

Forward Voltage Drop

We successfully fabricated 13-kV, 20-A, 8 mm × 8 mm, drift-free 4H-SiC PiN diodes. The fabricated diodes exhibited breakdown voltages that exceeded 13 kV, a forward voltage drop of 4.9–5.3 V, and an on-resistance (RonAactive) of 12 mW·cm2. The blocking yield at 10 kV on a 3-in wafer exceeded 90%. We investigated failed devices using Candela defect maps and light-emission images and found that a few devices failed because of large defects on the chip. We also demonstrated that the fabricated diodes can be used in conducting high-voltage and high-current switching tests.

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Low Temperature Thin-film Silicon Diodes for Consumer Electronics

MRS Proceedings ◽

10.1557/proc-862-a15.5 ◽

2005 ◽

Vol 862 ◽

Cited By ~ 1

Author(s):

Qi Wang ◽

Scott Ward ◽

Anna Duda ◽

Jian Hua ◽

Paul Stradins ◽

...

Keyword(s):

Thin Film ◽

Low Temperature ◽

Current Density ◽

Voltage Drop ◽

High Current Density ◽

Consumer Electronics ◽

High Current ◽

Plastic Substrates ◽

Forward Current ◽

Thin Film Silicon

AbstractWe have developed high current density thin-film silicon n-i-p diodes for low cost and low temperature two-dimensional diode-logic memory array applications. The diodes are fabricated at temperatures below 250°C on glass, stainless steel, and plastic substrates using hot-wire chemical vapor deposition (CVD). The 0.01-mm2 standalone diodes have a forward current-density (J) of near 10 kA/cm2 and a rectification ratio over 107 at ±2 V. The 25 μm2 array diodes have J > 104 A/cm2 and rectification of 105 at ±2V. On plastic substrates, we have also used plasma-enhanced CVD to deposit 10-μm diameter diodes with J ˜ 5 x 104 A/cm2. We found that the use of microcrystalline silicon (μc-Si) i- and nlayers results in higher current-density diodes than with amorphous silicon. Reducing the diode area increases the forward current density by lowering the voltage drop across the external series resistances. A prototype diode array memory based on 10-micron devices was successfully demonstrated by monolithically integrating diodes with a-Si:H switching elements. High current density diodes have potential applications in a variety of large area, thin-film electronic devices, in addition to a-Si:H-based memory. This could widen the application of thin-film silicon beyond its present industrial applications in thin-film transistors, solar cells, bolometers and photo-detectors.

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1600 V, 5.1 mΩ●cm2 4H-SiC BJT with a High Current Gain of β=70

Materials Science Forum ◽

10.4028/www.scientific.net/msf.600-603.1155 ◽

2008 ◽

Vol 600-603 ◽

pp. 1155-1158 ◽

Cited By ~ 11

Author(s):

Jian Hui Zhang ◽

Petre Alexandrov ◽

Jian Hui Zhao

Keyword(s):

High Performance ◽

Voltage Drop ◽

High Gain ◽

Current Gain ◽

High Current ◽

Large Area ◽

Collector Current ◽

Forward Voltage Drop ◽

Ac Current ◽

Dc Current

This paper reports a newly achieved best result on the common emitter current gain of 4H-SiC high power bipolar junction transistors (BJTs). A fabricated 1600 V – 15 A 4H-SiC power BJT with an active area of 1.7 mm2 shows a high DC current gain (b) of 70, when it conducts 9.8 A collector current at a base current of only 140 mA. The maximum AC current gain (DIC/DIB) is up to 78. This high performance BJT has an open base collector-to-emitter blocking voltage (VCEO) of over 1674 V with a leakage current of 1.6 μA, and a specific on-resistance (RSP-ON) of 5.1 mW.cm2 when it conducts 7.0 A (412 A/cm2) at a forward voltage drop of VCE = 2.1 V. A large area 4H-SiC BJT with a footprint of 4.1 mm x 4.1 mm has also shown a DC current gain over 50. These high-gain, high-voltage and high-current 4H-SiC BJTs further support a promising future for 4H-SiC BJT applications.

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Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.24.12145 ◽

2018 ◽

Vol 7 (2.24) ◽

pp. 496

Author(s):

Srinath B ◽

P Aruna priya ◽

Chirag Kasliwal

Keyword(s):

Fourier Transform ◽

Integrated Circuits ◽

Fast Fourier Transform ◽

Supply Voltage ◽

Voltage Drop ◽

Fir Filter ◽

Charge Carriers ◽

High Current ◽

Current Densities ◽

Electron Migration

In Contemporary Integrated Circuits (IC), the Voltage drop in the power rails and Electron migration risk (EM) due to high current densities are the most important factors degrading the reliability of the chip. The effect of these factors leads to an imbalance in the flow of charge carriers and voids in interconnects. This paper resolves the above issues, through analyzing and predetermining it in a Multiple Supply Voltage (MSV) design during the floorplanning stage. Simulations were carried out in Cadence digital Encounter system with 180nm technology for the circuit net list of 8 point FFT (Fast Fourier Transform) and FIR filter. Results show that floorplanning scheme is powerful in reducing 100% of voltage drop and 50% of EM risk in the chip as compared to previous works.

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