Fabrication of Al-Based Superconducting High-Aspect Ratio TSVS for Quantum 3D Integration

Integration in the third dimension is becoming increasingly more common in advanced packaging to overcome limitations in Moore's Law. One popular example for 3D Integration is Package-on-Package (PoP), where memory stacks are mounted above the processor. This approach requires tall, high density Cu pillars for interconnection around the processor. Ever increasing I/O requirements creates a need for Cu pillars with smaller critical dimension (CD) in thick resist. This creates high aspect ratio challenges for materials and equipment. For lithography tools, low NA projection systems are fundamentally well-suited to achieve high aspect ratio patterns, due to the inverse relationship between depth-of-focus (DOF) and Numerical Aperture (NA). However, the NA of low NA steppers is not low enough for thick resists. The full-field projection scanner with lower NA provides superior performance than the stepper counterpart at higher throughput and lower cost. This paper presents the high aspect ratio performance of the full-field UV projection scanner tool in various thick resists ranging from 50um to 300um film thickness. Aspect ratios as high as 20:1 are demonstrated for square vias with 1:1 pitch. Further, as feature resolution is only practical with alignment, the alignment of thick resists is also included.

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Double-Densified Vertically Aligned Carbon Nanotube Bundles for Application in 3D Integration High Aspect Ratio TSV Interconnects

2016 IEEE 66th Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2016.160 ◽

2016 ◽

Cited By ~ 1

Author(s):

Wei Mu ◽

Josef Hansson ◽

Shuangxi Sun ◽

Michael Edwards ◽

Yifeng Fu ◽

...

Keyword(s):

Carbon Nanotube ◽

Aspect Ratio ◽

High Aspect Ratio ◽

3D Integration ◽

Nanotube Bundles ◽

Vertically Aligned

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High aspect ratio via metallization for 3D integration using CVD TiN barrier and electrografted Cu seed

Microelectronic Engineering ◽

10.1016/j.mee.2008.06.004 ◽

2008 ◽

Vol 85 (10) ◽

pp. 1957-1961 ◽

Cited By ~ 23

Author(s):

G. Druais ◽

G. Dilliway ◽

P. Fischer ◽

E. Guidotti ◽

O. Lühn ◽

...

Keyword(s):

Aspect Ratio ◽

High Aspect Ratio ◽

3D Integration

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Low temperature MOCVD TiN barrier deposition for high aspect ratio TSVs : A solution for 3D integration

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2013dpc-wp12 ◽

2013 ◽

Vol 2013 (DPC) ◽

pp. 001322-001342 ◽

Cited By ~ 2

Author(s):

Thierry MOURIER ◽

Stephane Minoret ◽

Sabrina Fadloun ◽

Larissa Djomeni ◽

Sylvain Maitrejean ◽

...

Keyword(s):

Low Temperature ◽

Aspect Ratio ◽

High Aspect Ratio ◽

High Stress ◽

Integration Scheme ◽

3D Integration ◽

Good Efficiency ◽

Process Step ◽

Copper Diffusion ◽

Step Coverage

In recent years, 3D integration has become an alternative solution to the “More Moore” concept for providing circuits with higher performance or increased functionality. Via-Middle TSV is considered a reference integration scheme and requires void-free copper fill of very high aspect ratio TSVs. Metallization of such structures, in particular barrier and seed layer deposition, becomes a critical process step as barrier material to copper diffusion must provide good efficiency to copper diffusion for further integration and especially on TSV sidewalls, requiring sufficient step coverage. Ionized PVD is today widely extended from BEOL to TSV metallization. This technique has, however , several limitations for 3D integration coming from its poor step coverage in 10:1 aspect ratio features thus requiring thick material deposition to cover sidewalls which will lead to expensive process both for deposition and further CMP steps and high stress leading to adhesion issues. Considering the maturity level of the alternative processes, MOCVD metallization appears to be a very promising Solution. MOCVD TiN layers have been widely reported to provide excellent step coverage and diffusion barrier efficiency in BEOL processes. The presented study describes a process based on an MOCVD TiN deposition that can be performed from 175 to 400 °C. This polyvalent process can be performed for anytype of 3D integration from Mid process TSVs where performance is the key factor to Via last integration for which low temperature and low cost processes are required. The paper will first discuss the process development and characterization of this material with particular focus on key parameters for 3D integration. In addition, film integration in Via-Middle TSVs will be described, comparing step coverage performance in high aspect ratio TSVs with the I-PVD reference process. Then, electrical measurements of daisy chains and interconnect lines from a 300 mm 3D demonstrator will be presented.

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