scholarly journals A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology

2012 ◽  
Vol 3 (5) ◽  
pp. 157-162 ◽  
Author(s):  
R.H Talwekar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
Positive Edge ◽  
Frequency Detector

An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

1996 ◽  
Vol 31 (9) ◽  
pp. 1361-1363 ◽  
Author(s):  
T. Maeda ◽  
K. Numata ◽  
M. Fujii ◽  
M. Tokushima ◽  
S. Wada ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Low Power Consumption ◽  
Flip Flop ◽  
Ultra Low Power

Novel high-speed flip-flop circuit with low power consumption using GaAs junction FETs

1991 ◽  
Vol 27 (9) ◽  
pp. 764
Author(s):  
C. Takano ◽  
M. Wada ◽  
J. Kasahara
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Low Power Consumption ◽  
Flip Flop

PVT Aware Design of a Dead-zone Free High Speed Phase Frequency Detector in 90nm CMOS

2020 ◽  
Vol 13 (4) ◽  
pp. 516-530
Author(s):  
Suraj K. Saw ◽  
Madhusudan Maiti ◽  
Preetisudha Meher ◽  
Alak Majumder
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Speed ◽  
Dead Zone ◽  
Cmos Technology ◽  
Switching Noise ◽  
Phase Frequency Detector ◽  
Layout Area ◽  
Frequency Detector ◽  
Lock In

Background & Introduction: With the advent of technology, though the literature highlights many designs of Phase Frequency Detector (PFD), there remains some challenges like area overhead, switching noise near frequency lock point and fast, accurate response to mitigate dead zone and output errors. Methods: In this article, we have unearthed a low power, high speed and dead zone free PFD, which eliminates the switching noise near that lock-in node. This simple design uses lesser number of transistors to obtain smaller estimated layout area of 0.748mm2 and low power of 496.12μW, when operated at 10 GHz frequency at a power supply of 1.8V in 90nm CMOS technology. Results: The simulation reads a phase noise and output noise of -113.142dBc/Hz and -180.712dB at 1MHz offset. The circuit not only runs at a frequency as high as 40GHz, but also compatible to be operated at a power supply of as small as 0.9V. Conclusion: Process Variation analysis performed proves the robustness of the proposed circuit at all process corners. Also, the design gets validated at lower process nodes like 28nm UMC.

scholarly journals Implementation of Phase Frequency Detector in Phase locked loop using Preset able modified TSPC D flip-flop

2019 ◽  
Vol 8 (12) ◽  
pp. 977-980
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Single Phase ◽  
Phase Locked Loop ◽  
Frequency Multiplier ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
Technology Applications ◽  
Phase Clock ◽  
Frequency Detector

Phase locked loop (PLL) forms an important part in many applications. Here design of PLL for frequency multiplier operation is considered. Frequency multiplier operation is implemented by using Preset able Modified Single Phase Clock (MTSPC) D flipflop logic circuits in Phase Frequency Detector (PFD). Preset able Modified Single Phase Clock (MTSPC) D flipflops functions at high speed with less power consumption. Noises in the form of glitches are introduced when a preset-able true single phase clocked D flipflop (TSPC) used in Phase Locked Loop. Preset-able modified TSPC (MTSPC) D flipflop used to overcome these glitches caused due to toggling at the output by use of PMOS. Technology applied is 90nm technology. Applications where better speed and reduced power consumption are required, this type of Phase locked loop (PLL) can be utilized.

scholarly journals A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition

2011 ◽  
Vol 2011 ◽  
pp. 1-7
Author(s):  
Seon-Kyoo Lee ◽  
Young-Sang Kim ◽  
Hong-June Park ◽  
Jae-Yoon Sim
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Data Stream ◽  
Input Data ◽  
Low Power Consumption ◽  
Automatic Frequency ◽  
Automatic Tracking ◽  
Phase Frequency Detector ◽  
Simple Phase ◽  
Frequency Detector

A wide lock-range referenceless CDR circuit is proposed with an automatic tracking of data rate. For efficient frequency acquisition, a DLL-based loop is used with a simple phase/frequency detector to extract 1-bit period of input data stream. The CDR, implemented in a 65 nm CMOS, shows a lock range of 650 Mb/s-to-8 Gb/s and BER of less than 10-12at 8 Gb/s with low power consumption.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

scholarly journals A high-speed hybrid Full Adder with low power consumption

2012 ◽  
Vol 9 (24) ◽  
pp. 1900-1905
Author(s):  
Kamran Delfan Hemmati ◽  
Mojtaba Behzad Fallahpour ◽  
Abbas Golmakani ◽  
Kamyar Delfan Hemmati
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Full Adder ◽  
Low Power Consumption

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

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