Background & Introduction:
With the advent of technology, though the literature highlights
many designs of Phase Frequency Detector (PFD), there remains some challenges like area
overhead, switching noise near frequency lock point and fast, accurate response to mitigate dead
zone and output errors.
Methods:
In this article, we have unearthed a low power, high speed and dead zone free PFD,
which eliminates the switching noise near that lock-in node. This simple design uses lesser number
of transistors to obtain smaller estimated layout area of 0.748mm2 and low power of 496.12μW,
when operated at 10 GHz frequency at a power supply of 1.8V in 90nm CMOS technology.
Results:
The simulation reads a phase noise and output noise of -113.142dBc/Hz and -180.712dB
at 1MHz offset. The circuit not only runs at a frequency as high as 40GHz, but also compatible to
be operated at a power supply of as small as 0.9V.
Conclusion:
Process Variation analysis performed proves the robustness of the proposed circuit at
all process corners. Also, the design gets validated at lower process nodes like 28nm UMC.
A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology
