Low power Null Convention Logic circuit design based on DCVSL

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2013.6674577 ◽

2013 ◽

Author(s):

Ho Joon Lee ◽

Yong-Bin Kim

Keyword(s):

Low Power ◽

Circuit Design ◽

Logic Circuit ◽

Null Convention Logic

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A Novel Low-Power Logic Circuit Design Scheme

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ◽

10.1109/tcsii.2006.883093 ◽

2007 ◽

Vol 54 (2) ◽

pp. 176-180 ◽

Author(s):

Janusz A. Starzyk ◽

Haibo He

Keyword(s):

Low Power ◽

Circuit Design ◽

Logic Circuit ◽

Design Scheme ◽

Low Power Logic

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Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea5020081 ◽

2015 ◽

Vol 5 (2) ◽

pp. 81-100 ◽

Author(s):

Liang Zhou ◽

Ravi Parameswaran ◽

Farhad Parsan ◽

Scott Smith ◽

Jia Di

Keyword(s):

Low Power ◽

Circuit Design ◽

Design Methodology ◽

Asynchronous Circuit ◽

Ultra Low Power ◽

Null Convention Logic ◽

Asynchronous Circuit Design

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Gate Diffusion Input Multi-Threshold Null Convention Logic Circuit Design Approach

2020 International SoC Design Conference (ISOCC) ◽

10.1109/isocc50952.2020.9332941 ◽

2020 ◽

Author(s):

Prashanthi Metku ◽

Minsu Choi ◽

Kyung-Ki Kim ◽

Yong-Bin Kim

Keyword(s):

Circuit Design ◽

Logic Circuit ◽

Design Approach ◽

Null Convention Logic

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Silicon on insulator null convention logic based asynchronous circuit design for high performance low power digital systems

2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications & Computing (SigTelCom) ◽

10.1109/sigtelcom.2018.8325772 ◽

2018 ◽

Author(s):

Nguyen Le Huy ◽

Anthony S. Holland ◽

Paul Beckett

Keyword(s):

Low Power ◽

Circuit Design ◽

High Performance ◽

Silicon On Insulator ◽

Digital Systems ◽

Asynchronous Circuit ◽

Null Convention Logic ◽

Asynchronous Circuit Design

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Low power dynamic logic circuit design using a pseudo dynamic buffer

Integration ◽

10.1016/j.vlsi.2011.08.003 ◽

2012 ◽

Vol 45 (4) ◽

pp. 395-404 ◽

Author(s):

Fang Tang ◽

Amine Bermak ◽

Zhouye Gu

Keyword(s):

Low Power ◽

Circuit Design ◽

Dynamic Logic ◽

Logic Circuit ◽

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Low-power High-speed Complementary Gaas Dynamic Logic Circuit Design

Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications ◽

10.1109/vtsa.1997.614910 ◽

2005 ◽

Author(s):

K.A. Shehata ◽

D.J. Fouts

Keyword(s):

Low Power ◽

Circuit Design ◽

Dynamic Logic ◽

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Tunable Delay Element for Low Power VLSI Circuit Design

TENCON 2006 - 2006 IEEE Region 10 Conference ◽

10.1109/tencon.2006.344092 ◽

2006 ◽

Author(s):

Jung-Lin Yang ◽

Chih-Wei Chao ◽

Sung-Min Lin

Keyword(s):

Low Power ◽

Circuit Design ◽

Vlsi Circuit ◽

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Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581) ◽

10.1145/383082.383136 ◽

2001 ◽

Author(s):

Rongtian Zhang ◽

Kaushik Roy ◽

David Janes

Keyword(s):

Low Power ◽

Circuit Design ◽

High Performance ◽

Double Gate ◽

Fully Depleted ◽

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Low power supply BiCMOS SRAM circuit design issues

[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.1992.271258 ◽

2003 ◽

Author(s):

H. van Tran

Keyword(s):

Low Power ◽

Circuit Design ◽

Power Supply ◽

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Low-power analog/RF circuit design based on the inversion coefficient

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) ◽

10.1109/esscirc.2015.7313863 ◽

2015 ◽

Author(s):

Christian Enz ◽

Maria-Anna Chalkiadaki ◽

Anurag Mangla

Keyword(s):

Low Power ◽

Circuit Design ◽

Inversion Coefficient ◽

Rf Circuit Design ◽

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