An In-Situ Sliding Window Approximate Inner-Product Scheme Based on Parallel Distributed Arithmetic for Ultra-Low Power Fault-Tolerant Applications

This paper briefs an area efficient, low power and high throughput LMS adaptive filter using Distributed Arithmetic architecture. The throughput is increased because of parallel updating of filter coefficient and computing the inner product simultaneously. Here we have proposed memory-less design of distributed arithmetic (MLDA) unit. The proposed design uses 2:1 multiplexer’s architecture to replace LUT of the conventional DA to reduce the overall area of the filter. Enhanced compressor adder is used for accumulation of the partial products, which further helps to reduce the area. Parallel updating of the generation and accumulation enhance the throughput of the design. The proposed architecture requires more than half area that required for the existing LUT based inner product block. The proposed design is implemented in synopsis design compiler and the result shows that the area decreased by 52.7% and also the MUX based DA for the Adaptive filter causes 69.25% less power consumption for filter tap N=16, 32 and 64. Proposed design provides 36.50% less Area Delay Product (ADP).

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Fault Tolerant Approaches Targeting Ultra Low Power Communications System Design

2007 IEEE 65th Vehicular Technology Conference - VTC2007-Spring ◽

10.1109/vetecs.2007.535 ◽

2007 ◽

Cited By ~ 6

Author(s):

Amin Khajeh Djahromi ◽

Ahmed M. Eltawil ◽

Fadi J. Kurdahi

Keyword(s):

Low Power ◽

System Design ◽

Fault Tolerant ◽

Ultra Low Power ◽

Communications System

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Low-Power OR Logic Ferroelectric In Situ Transistor Based on a CuInP2S6/MoS2 Van Der Waals Heterojunction

Nanomaterials ◽

10.3390/nano11081971 ◽

2021 ◽

Vol 11 (8) ◽

pp. 1971

Author(s):

Kun Yang ◽

Shulong Wang ◽

Tao Han ◽

Hongxia Liu

Keyword(s):

Low Power ◽

Supply Voltage ◽

Field Effect Transistors ◽

Van Der Waals ◽

Boltzmann Distribution ◽

Ferroelectric Materials ◽

Subthreshold Swing ◽

Ultra Low Power ◽

Field Amplification

Due to the limitations of thermodynamics, the Boltzmann distribution of electrons hinders the further reduction of the power consumption of field-effect transistors. However, with the emergence of ferroelectric materials, this problem is expected to be solved. Herein, we demonstrate an OR logic ferroelectric in-situ transistor based on a CIPS/MoS2 Van der Waals heterojunction. Utilizing the electric field amplification of ferroelectric materials, the CIPS/MoS2 vdW ferroelectric transistor offers an average subthreshold swing (SS) of 52 mV/dec over three orders of magnitude, and a minimum SS of 40 mV/dec, which breaks the Boltzmann limit at room temperature. The dual-gated ferroelectric in-situ transistor exhibits excellent OR logic operation with a supply voltage of less than 1 V. The results indicate that the CIPS/MoS2 vdW ferroelectric transistor has great potential in ultra-low-power applications due to its in-situ construction, steep-slope subthreshold swing and low supply voltage.

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Design & Analysis of Novel Non-Reversible & Reversible Parity Generator & Detector in Quantum Cellular Automata using Feynman Gate

Micro and Nanosystems ◽

10.2174/1876402913666210726170207 ◽

2021 ◽

Vol 13 ◽

Author(s):

Neeraj Tripathi ◽

Mohammad Mudakir Fazili ◽

Rahil Jahangir

Keyword(s):

Energy Dissipation ◽

Cellular Automata ◽

Quantum Dot ◽

Low Power ◽

Fault Tolerant ◽

Design Parameters ◽

Logic Function ◽

Ultra Low Power ◽

Quantum Dot Cellular Automata ◽

Parity Generator

Aim: A novel design for non-reversible as well as reversible parity generator and detector in Quantum-dot Cellular Automata (QCA) technology is presented in this research article. Parity generator and detector circuits are reliable error-checking components of a nano-communication system. Objective: The main focus of this research is to design an ultra-low-power fault-tolerant reversible gate implementation of the parity logic function in QCA. An efficient QCA design layout with minimal area, less latency and the least energy dissipation is desired. Methods: The proposed designs are developed using Quantum-dot Cellular Automata (QCA) technology. The circuits are optimized using majority gate reduction and clock zone reduction techniques. Also, the cell-cell interaction technique is employed to further optimize the QCA circuit. To increase the fault tolerance and for ultra-low power operation, reversible QCA circuits are designed using cascaded Feynman gates. Results and Conclusion: The efficiency of the parity generator and detector is calculated to be more than 25% compared to existing QCA layouts. It is demonstrated in this paper that the proposed circuits perform exceptionally well on every design parameter. The design parameters under consideration are cell count, cell area, complexity, crossover count, latency and energy dissipation. Using reversible logic, a fault-tolerant and defect-sensitive circuit is developed for parity generation and detection.

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