Device parameter fluctuations, which arise from both the stochastic nature of the manufacturing process and more fundamentally from the intrinsic discreteness of charge and matter, are a dominant source of device mismatch in nano-CMOS devices, and a bottleneck to the future yield and performance of circuits and systems. The impact of such parameter fluctuations is investigated for circuits — with a specific exemplar of 6-T SRAM — whose devices scale from 35 nm gate length. We posit a change in design approach to include the use of statistical compact models as a starting point for the development of cell libraries containing fluctuation information necessary for design under the constraints of parameter fluctuations, and novel Technology Aided System Design tools.