Supervised training of spiking neural networks for robust deployment on mixed-signal neuromorphic processors

Mixed-signal analog/digital circuits emulate spiking neurons and synapses with extremely high energy efficiency, an approach known as “neuromorphic engineering”. However, analog circuits are sensitive to process-induced variation among transistors in a chip (“device mismatch”). For neuromorphic implementation of Spiking Neural Networks (SNNs), mismatch causes parameter variation between identically-configured neurons and synapses. Each chip exhibits a different distribution of neural parameters, causing deployed networks to respond differently between chips. Current solutions to mitigate mismatch based on per-chip calibration or on-chip learning entail increased design complexity, area and cost, making deployment of neuromorphic devices expensive and difficult. Here we present a supervised learning approach that produces SNNs with high robustness to mismatch and other common sources of noise. Our method trains SNNs to perform temporal classification tasks by mimicking a pre-trained dynamical system, using a local learning rule from non-linear control theory. We demonstrate our method on two tasks requiring temporal memory, and measure the robustness of our approach to several forms of noise and mismatch. We show that our approach is more robust than common alternatives for training SNNs. Our method provides robust deployment of pre-trained networks on mixed-signal neuromorphic hardware, without requiring per-device training or calibration.

Design and Device Mismatch Analysis of CSS–UWB Pulse Generator

This paper presents the design of a Chirp Spread Spectrum (CSS), ultra-wideband (UWB), pulse generator (PG) and device mismatch impact on its performance. The proposed CSS-PG is built using a differential ring oscillator (RO) controlled by a ramp generator, allowing varying linearly the pulse frequency with time over the CSS pulse duration. Device mismatches and random variations during integrated circuit manufacturing are the most critical imperfections in high precision differential UWB voltage controlled RO circuit. These mismatches lead to behavioral variations of the PG. The proposed CSS-UWB-PG is designed and analyzed using CMOS 0.18[Formula: see text][Formula: see text]m technology. The CSS-PG presents an output swing of 266[Formula: see text]mV Vpp for 20[Formula: see text]nsec and consumes 1.72[Formula: see text]mW for a PRF of 10[Formula: see text]MHz. The simulated PSD covers the UWB low band from 3[Formula: see text]GHz to 5[Formula: see text]GHz and complies with the FCC regulations. For [Formula: see text] mismatch, the simulation results show a maximum relative accuracy on oscillation frequency and phase noise of 3.43% and 6.9%, respectively. Monte Carlo and process simulation are performed to study the impact of the random parameter variation on this CSS-PG. Theses simulations show the robustness of the proposed design as the PG PSD is still inside the FCC-UWB mask and its bandwidth is greater than 500[Formula: see text]MHz.

Performing Memristor-Aided Logic (MAGIC) using STT-MRAM

—Modern computers suffer from a limited data transfer rate between the memory and the processing units. One of the attractive potential solutions to overcome this bottleneck is to combine processing and memory by performing computing in the same location where the data is stored. Processing-in-memory (PIM) has been demonstrated by memristor-aided logic (MAGIC) operations using resistive random access memory (RRAM) memristive devices within crossbar arrays. Nevertheless, RRAM devices are relatively slow and suffer from limited endurance. Spin-transfer torque magnetoresistive random access memory (STT-MRAM) is another memristive technology, which is faster and has practically unlimited endurance and is therefore considered to be an attractive technology for cache-level memories. In this paper, we demonstrate MAGIC operations within an STT-MRAM array by supplying voltages suitable to achieve the current required for MRAM device switching. The proposed circuit was evaluated in SPICE simulations with the GlobalFoundries 22nm CMOS-MRAM process, including Monte Carlo simulations to verify the proposed design in the presence of process variation and device mismatch. The circuit showed more than 90% chance of functioning for the {1 1} and {0 0} input cases while it was about 85% correct for the {0 1} case.

Performing Memristor-Aided Logic (MAGIC) using STT-MRAM

—Modern computers suffer from a limited data transfer rate between the memory and the processing units. One of the attractive potential solutions to overcome this bottleneck is to combine processing and memory by performing computing in the same location where the data is stored. Processing-in-memory (PIM) has been demonstrated by memristor-aided logic (MAGIC) operations using resistive random access memory (RRAM) memristive devices within crossbar arrays. Nevertheless, RRAM devices are relatively slow and suffer from limited endurance. Spin-transfer torque magnetoresistive random access memory (STT-MRAM) is another memristive technology, which is faster and has practically unlimited endurance and is therefore considered to be an attractive technology for cache-level memories. In this paper, we demonstrate MAGIC operations within an STT-MRAM array by supplying voltages suitable to achieve the current required for MRAM device switching. The proposed circuit was evaluated in SPICE simulations with the GlobalFoundries 22nm CMOS-MRAM process, including Monte Carlo simulations to verify the proposed design in the presence of process variation and device mismatch. The circuit showed more than 90% chance of functioning for the {1 1} and {0 0} input cases while it was about 85% correct for the {0 1} case.