Modified Geffe Test Pattern Generator for Built-in Self-test

2007 ◽  
Author(s):  
Dandan Qi ◽  
Jon C. Muzio
Keyword(s):  
Test Pattern ◽  
Pattern Generator ◽  
Self Test ◽  
Built In Self Test

Weighted Cellular Automata Design for Test Pattern Generator Based on Genetic Algorithm

2013 ◽  
Vol 273 ◽  
pp. 840-844 ◽  
Author(s):  
En Min Tan ◽  
Qing Qing Li ◽  
Ji Gang Jiang
Keyword(s):  
Cellular Automata ◽  
Test Pattern ◽  
Pattern Generator ◽  
Fault Coverage ◽  
Test Design ◽  
Design For Test ◽  
Test Length ◽  
Vlsi Test ◽  
Self Test ◽  
Built In Self Test

In built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test length, fault coverage and test consumption, etc. A one-dimension hybrid cellular automata (CA) is used as the core of test pattern generator, with an optimization of its rules based on multi-objectives evolution algorithm. A certain rule which selected from the optimized rule set is adopted to form the weighted cellular automata, by the using of verilog HDL. Experiment results was obtained by simulation of some ISCAS’8n built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test le5 benchmark circuits, and indicated that the test length was reduced obviously (at a ratio above 60%), without losing fault coverage (within a discrepancy of 3%); moreover, the power consumption would be decreased correspondingly.

Built-in Self-Test Design for Fault Detection of MUXFXs in SRAM-Based FPGAs

2010 ◽  
Vol 39 ◽  
pp. 220-225
Author(s):  
Sheng Hong ◽  
Wen Hui Tao ◽  
Yun Ping Qi ◽  
Cheng Gao ◽  
Xiao Zhang Liu ◽  
...  
Keyword(s):  
Fault Detection ◽  
Test Pattern ◽  
Pattern Generator ◽  
Test Design ◽  
Output Response ◽  
Area Overhead ◽  
Self Test ◽  
Built In Self Test ◽  
Logic Blocks

This paper proposes a built-in self-test (BIST) design for MUXFXs in SRAM-based FPGAs. This approach can test both the interconnect resources and MUXFXs in the configurable logic blocks (CLBs). Because the test pattern generator (TPG) and output response analyzer (ORA)are configured by existing CLBs in FPGAs, no extra area overhead is needed for the proposed BIST structure. Open/short , stuck on/off faults in PSs, and stuck-at-0/1 faults in MUXFXs will be detected through the target fault detection/diagnosis of the proposed BIST structure.

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