A low jitter wide tuning range phase locked loop with low power consumption in 180nm CMOS technology

Author(s):  
S. Aditya ◽  
S. Moorthi
Author(s):  
Norio Okada ◽  
Shiho Zaizen ◽  
Atsushi Sugitatsu ◽  
Tatsuo Hatta ◽  
Takeshi Fujita ◽  
...  

2013 ◽  
Vol 411-414 ◽  
pp. 125-130
Author(s):  
Yan Bo Niu ◽  
An Ping Jiang

SM4 is a 128-bit block cipher used in SOC and smart cards to ensure the safety of data transmission. In order to realize a low power implementation of the SM4 cipher block, some S-boxes were evaluated firstly and we proposed a new architecture of SM4 S-box called MUX S-box with a power consumption of 13.92W@10Mhz on SMIC 0.18m technology, Meanwhile, the implementation of SM4 cipher round based on the SM4 MUX S-box was completed and a low power consumption of 0.33mW @ 10 MHz on 0.18 m CMOS technology is achieved.


2020 ◽  
Vol 6 (18) ◽  
pp. eaaz6511 ◽  
Author(s):  
Gongjin Li ◽  
Zhe Ma ◽  
Chunyu You ◽  
Gaoshan Huang ◽  
Enming Song ◽  
...  

The sensing module that converts physical or chemical stimuli into electrical signals is the core of future smart electronics in the post-Moore era. Challenges lie in the realization and integration of different detecting functions on a single chip. We propose a new design of on-chip construction for low-power consumption sensor, which is based on the optoelectronic detection mechanism with external stimuli and compatible with CMOS technology. A combination of flipped silicon nanomembrane phototransistors and stimuli-responsive materials presents low-power consumption (CMOS level) and demonstrates great functional expansibility of sensing targets, e.g., hydrogen concentration and relative humidity. With a device-first, wafer-compatible process introduced for large-scale silicon flexible electronics, our work shows great potential in the development of flexible and integrated smart sensing systems for the realization of Internet of Things applications.


2019 ◽  
Vol 8 (4) ◽  
pp. 3994-3999

For high speed communication applications; jitter, phase noise and power consumption are most critical parameters required to be considered for PLL designs. A sub harmonically injection locking concept can be used in PLL to reduce jitter and phase noise. Such design is very effective for high frequency applications. This article presents similar design for 7.5-GHz Phase locked loop in 180 nm CMOS technology. The measured phase noise of the proposed PLL with self aligned injection at 1 MHz offset is 121.14 dBc/Hz and rms jitter is 110 fs. The total dc power consumption is 13.99 mW. To support the claim process variation with design corner analysis using random variations are carried out.


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