scholarly journals Silicon nanomembrane phototransistor flipped with multifunctional sensors toward smart digital dust

2020 ◽  
Vol 6 (18) ◽  
pp. eaaz6511 ◽  
Author(s):  
Gongjin Li ◽  
Zhe Ma ◽  
Chunyu You ◽  
Gaoshan Huang ◽  
Enming Song ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Flexible Electronics ◽  
Large Scale ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Stimuli Responsive ◽  
Single Chip ◽  
Detection Mechanism ◽  
Silicon Nanomembrane

The sensing module that converts physical or chemical stimuli into electrical signals is the core of future smart electronics in the post-Moore era. Challenges lie in the realization and integration of different detecting functions on a single chip. We propose a new design of on-chip construction for low-power consumption sensor, which is based on the optoelectronic detection mechanism with external stimuli and compatible with CMOS technology. A combination of flipped silicon nanomembrane phototransistors and stimuli-responsive materials presents low-power consumption (CMOS level) and demonstrates great functional expansibility of sensing targets, e.g., hydrogen concentration and relative humidity. With a device-first, wafer-compatible process introduced for large-scale silicon flexible electronics, our work shows great potential in the development of flexible and integrated smart sensing systems for the realization of Internet of Things applications.

A Low Power Design of SM4 Cipher Based on MUX S-Box Architecture

2013 ◽  
Vol 411-414 ◽  
pp. 125-130
Author(s):  
Yan Bo Niu ◽  
An Ping Jiang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Data Transmission ◽  
Block Cipher ◽  
Low Power Design ◽  
Cmos Technology ◽  
Smart Cards ◽  
Low Power Consumption

SM4 is a 128-bit block cipher used in SOC and smart cards to ensure the safety of data transmission. In order to realize a low power implementation of the SM4 cipher block, some S-boxes were evaluated firstly and we proposed a new architecture of SM4 S-box called MUX S-box with a power consumption of 13.92W@10Mhz on SMIC 0.18m technology, Meanwhile, the implementation of SM4 cipher round based on the SM4 MUX S-box was completed and a low power consumption of 0.33mW @ 10 MHz on 0.18 m CMOS technology is achieved.

scholarly journals Low Power Consumption Digital Clock Recovery Circuit Based on Threshold Crossing

2016 ◽  
Vol 67 (6) ◽  
pp. 433-438
Author(s):  
Dragana Perić ◽  
Miroslav Perić
Keyword(s):  
Mathematical Model ◽  
Power Consumption ◽  
Low Power ◽  
Phase Error ◽  
Low Complexity ◽  
Clock Recovery ◽  
Low Power Consumption ◽  
Single Chip ◽  
Digital Clock ◽  
Measurement Methodology

Abstract In this paper a new structure of digital clock recovery — DCR circuit is presented. The main features of this DCR are: low complexity design, low power consumption and a single system clock operation. Thus, multiple instantiation of this type of DCR on a single chip is not complex. Due to this, such DCR can target application in energy-efficient cognitive radio systems with carrier aggregation. For performance evaluation, we have derived Markov chain based mathematical model for peak-to-peak and root mean square jitter performance analysis. The stability problem of this model, rising from the fact that some phase error states have several orders of magnitude lower probabilities than the others, is solved using mathematical apparatus for symbolic analysis. The mathematical model validity is examined by laboratorial measurements of proposed DCR for 4-PAM signal. The measurement methodology and results are described in details.

Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques

2020 ◽  
Vol 17 (4) ◽  
pp. 1595-1599
Author(s):  
N. Suresh ◽  
K. Subba Rao ◽  
R. Vassoudevan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Large Scale ◽  
Digital Signal ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Essential Components

Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.

scholarly journals An efficient high speed, high frequency domino-logic based circuit

2018 ◽  
Vol 7 (2) ◽  
pp. 252
Author(s):  
Mahdi Zare ◽  
Hossein Manouchehrpour ◽  
Ahmad Esmaeilkhah
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Frequency ◽  
High Speed ◽  
Large Scale ◽  
Considerable Improvement ◽  
Low Power Consumption ◽  
Domino Logic ◽  
Large Scale Integration ◽  
Scale Integration

As the Very Large-Scale Integration (VLSI) techniques are mostly focused on high-speed and low power consumption circuits, various techniques and technologies were investigated to gain these two precious goals. Domino-logic is one of the circuits which is regarded to have high speed, high frequency and low power consumption. This work proposes a Domini logic circuit which has improved PDP compare to the previous one. The suggested circuit was simulated and the attained results show a considerable improvement in circuit’s speed in respect with its ancestor. The PDP of the circuit in 90 nm, biased at 1V, has been calculated as 53% approximately improvement. This improvement for PDP in 65 nm, 45 nm and 32 nm are 48%, 47% and 51% respectively.  

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