A Low Power Design of SM4 Cipher Based on MUX S-Box Architecture

2013 ◽  
Vol 411-414 ◽  
pp. 125-130
Author(s):  
Yan Bo Niu ◽  
An Ping Jiang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Data Transmission ◽  
Block Cipher ◽  
Low Power Design ◽  
Cmos Technology ◽  
Smart Cards ◽  
Low Power Consumption

SM4 is a 128-bit block cipher used in SOC and smart cards to ensure the safety of data transmission. In order to realize a low power implementation of the SM4 cipher block, some S-boxes were evaluated firstly and we proposed a new architecture of SM4 S-box called MUX S-box with a power consumption of 13.92W@10Mhz on SMIC 0.18m technology, Meanwhile, the implementation of SM4 cipher round based on the SM4 MUX S-box was completed and a low power consumption of 0.33mW @ 10 MHz on 0.18 m CMOS technology is achieved.

scholarly journals An Accurate Wireless Data Transmission and Low Power Consumption of Foot Plantar Pressure Measurements

2015 ◽  
Vol 76 ◽  
pp. 302-307 ◽  
Author(s):  
Aina Mardhiyah M. Ghazali ◽  
W.Z.W. Hasan ◽  
M.N. Hamidun ◽  
Ahmed H. Sabry ◽  
S.A. Ahmed ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Data Transmission ◽  
Plantar Pressure ◽  
Low Power Consumption ◽  
Pressure Measurements ◽  
Wireless Data ◽  
Wireless Data Transmission

Design of Wireless Intelligent Home Control System Based on Zigbee Technology

2013 ◽  
Vol 416-417 ◽  
pp. 900-903 ◽  
Author(s):  
Yu Hang Jiang ◽  
Hong Xia Yang
Keyword(s):  
Control System ◽  
Power Consumption ◽  
Low Power ◽  
Data Transmission ◽  
Intelligent System ◽  
Reaction Time Data ◽  
Low Power Consumption ◽  
Time Data ◽  
Intelligent Home ◽  
Zigbee Technology

Zigbee technology is a kind of bi-directional wireless communication technology characterized by close distance, low complexity, low power consumption, low speed and low cost. It is mainly used for data transmission of various electronic equipments with short distance, low power consumption and low transmission speed, as well as application of typical periodic data, intermittent data and low reaction time data transmission. This thesis first of all makes an analysis of characteristics of zigbee technology, based on which the design of wireless intelligent home control system based on zigbee technology is proposed. Finally, it gives an analysis of the daily management and maintenance of intelligent system, so as to contribute to further studies.

scholarly journals Silicon nanomembrane phototransistor flipped with multifunctional sensors toward smart digital dust

2020 ◽  
Vol 6 (18) ◽  
pp. eaaz6511 ◽  
Author(s):  
Gongjin Li ◽  
Zhe Ma ◽  
Chunyu You ◽  
Gaoshan Huang ◽  
Enming Song ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Flexible Electronics ◽  
Large Scale ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Stimuli Responsive ◽  
Single Chip ◽  
Detection Mechanism ◽  
Silicon Nanomembrane

The sensing module that converts physical or chemical stimuli into electrical signals is the core of future smart electronics in the post-Moore era. Challenges lie in the realization and integration of different detecting functions on a single chip. We propose a new design of on-chip construction for low-power consumption sensor, which is based on the optoelectronic detection mechanism with external stimuli and compatible with CMOS technology. A combination of flipped silicon nanomembrane phototransistors and stimuli-responsive materials presents low-power consumption (CMOS level) and demonstrates great functional expansibility of sensing targets, e.g., hydrogen concentration and relative humidity. With a device-first, wafer-compatible process introduced for large-scale silicon flexible electronics, our work shows great potential in the development of flexible and integrated smart sensing systems for the realization of Internet of Things applications.

scholarly journals Low Power Design of 2–4 and 4–16 Line Decoders

2019 ◽  
Vol 8 (9) ◽  
pp. 1220-1224
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Design ◽  
Low Power Consumption ◽  
Transmission Gate ◽  
Novel Design

Here, we are proposing a novel design of 2:4 decoder and 4:16 decoders which are designed by using line decoder concept. By using proposed design, the area and power consumption of 2:4 decoder and 4:16 decoder can be reduced. In the existing work they have used DVL (Dual Value Logic) and Transmission gate Logic to implement a 14-Transistor 2:4 decoder for minimizing the transistor count. By using 2:4 pre-decoders and post-decoders they implemented 4:16 decoders. Mixed logic is also used for this purpose. Here we have implemented a single 2:4 decoder with minimum transistor count and low power consumption which is used to design a 4:16 decoder. We implement the proposed design in Cadence Virtuoso simulation at 90nm technology and calculated the power and area.

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