Ultra-low voltage and low power UWB CMOS LNA using forward body biases

2013 ◽  
Author(s):  
Chih-Shiang Chang ◽  
Lyh-Chyurn Guo
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Cmos Lna

PVT ‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

2020 ◽  
Vol 30 (11) ◽  
Author(s):  
Sajad Nejadhasan ◽  
Fatemeh Zaheri ◽  
Ebrahim Abiri ◽  
Mohammad Reza Salehi
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Iot Applications ◽  
Low Power Cmos ◽  
Cmos Lna

scholarly journals Highly linear low voltage low power CMOS LNA

2013 ◽  
Vol 10 (21) ◽  
pp. 20130557-20130557 ◽  
Author(s):  
Ehsan Kargaran ◽  
Negar Zoka ◽  
Abbas Z. Kouzani ◽  
Khalil Mafinezhad ◽  
Hooman Nabovati
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Low Power Cmos ◽  
Cmos Lna

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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