A fully matched dual stage CMOS power amplifier with integrated passive linearizer attaining 23 db gain, 40% PAE and 28 DBM OIP3

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Premmilaah Gunasegaran ◽  
Jagadheswaran Rajendran ◽  
Selvakumar Mariappan ◽  
Yusman Mohd Yusof ◽  
Zulfiqar Ali Abdul Aziz ◽  
...  
Keyword(s):  
Power Consumption ◽  
Output Power ◽  
Power Amplifier ◽  
Maximum Output Power ◽  
Maximum Output ◽  
Power Gain ◽  
Matching Network ◽  
Content Type ◽  
Power Added Efficiency ◽  
Main Amplifier

Purpose The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA). Design/methodology/approach The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability. Findings With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation. Practical implications The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design. Originality/value The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

A 4.2-to-5.4 GHz stacked GaAs HBT power amplifier for C-band applications

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 243-248
Author(s):  
Min Liu ◽  
Panpan Xu ◽  
Jincan Zhang ◽  
Bo Liu ◽  
Liwen Zhang
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
High Power ◽  
High Efficiency ◽  
Common Source ◽  
Power Performance ◽  
Matching Network ◽  
Content Type ◽  
Power Added Efficiency ◽  
Saturated Output Power

Purpose Power amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential use in multi-band system implementation. The purpose of this paper is to present a cascode power amplifier architecture to achieve high power and high efficiency requirements for 4.2∼5.4 GHz applications. Design/methodology/approach A common emitter (CE) configuration with a stacked common base configuration of heterojunction bipolar transistor (HBT) is used to achieve high power. T-type matching network is used as input matching network. To increase the bandwidth, the output matching networks are implemented using the two L-networks. Findings By using the proposed method, the stacked PA demonstrates a maximum saturated output power of 26.2 dBm, a compact chip size of 1.17 × 0.59 mm2 and a maximum power-added efficiency of 46.3 per cent. The PA shows a wideband small signal gain with less than 3 dB variation over working frequency. The saturated output power of the proposed PA is higher than 25 dBm between 4.2 and 5.4 GHz. Originality/value The technology adopted for the design of the 4.2-to-5.4 GHz stacked PA is the 2-µm gallium arsenide HBT process. Based on the proposed method, a better power performance of 3 dB improvement can be achieved as compared with the conventional CE or common-source amplifier because of high output stacking impedance.

Design of a 0.7~2.6GHz Wideband Power Amplifier in 0.18-μm CMOS Process

2014 ◽  
Vol 618 ◽  
pp. 543-547
Author(s):  
Zhou Yu ◽  
Xiang Ning Fan ◽  
Zai Jun Hua ◽  
Chen Xu
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Negative Feedback ◽  
Maximum Output Power ◽  
Cmos Process ◽  
Maximum Output ◽  
Power Gain ◽  
Class A ◽  
Simulation Results ◽  
Multi Mode

A power amplifier (PA) for multi-mode multi-standard transceiver which is implemented in a TSMC 0.18μm process is presented. The proposed PA uses matching compensation, lossy matching network and negative feedback technique to improve bandwidth. To achieve the linearity performance, the two-stage PA operates in Class-A regime. Simulation results show that the power amplifier achieves maximum output power of more than 24dBm in 0.7~2.6GHz. The output P1dBof the PA is larger than 22dBm. The simulated power gain is more than 27dB. The S11 is less than-10dB and the S22 is under-5dB.

Concurrent dual-band SiGe HBT power amplifier for Wireless applications

2009 ◽  
Vol 1 (2) ◽  
pp. 117-126 ◽  
Author(s):  
Vittorio Camarchia ◽  
Rocco Giofrè ◽  
Iacopo Magrini ◽  
Luca Piazzon ◽  
Alessandro Cidronali ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Orthogonal Frequency Division Multiplexing ◽  
Maximum Output Power ◽  
System Level ◽  
Dual Band ◽  
Maximum Output ◽  
System Architectures ◽  
Power Added Efficiency ◽  
Mode Operation

This paper presents an investigation of a concurrent low-cost dual-band power amplifier (PA) fabricated in SiGe technology, able to simultaneously operate at two frequencies of 2.45 and 3.5-GHz, including an evaluation of its system level performance potentiality. Taking into account the technology novelty and the lack of device characterization and modeling, a hybrid (MIC) approach has been adopted both for a fast prototyping of the PA and for the evaluation of the device potentiality based on an extensive linear and nonlinear characterization. The comparison of PA performance in single-band or concurrent mode operation will be presented. In particular, the measured PA prototype shows an output power of 17.2 and 17-dBm at a 1-dB compression point, at 2.45 and 3.5-GHz, respectively, for CW single-mode operation, with a power added efficiency around 20%. System-level analysis predicts that, when the PA is operated under the 20-MHz Orthogonal Frequency-Division Multiplexing (OFDM) concurrent signals, the maximum output power levels to maintain the Error Vector Magnitude (EVM) within 5% are 11 and 3.5-dBm at 2.45 and 3.5-GHz, respectively. Moreover, new concepts and possible new system architectures for the development of the next generation of the multi-band transceiver front-end will be provided with an extensive system-level evaluation of the amplifier.

scholarly journals A Novel Configuration of A Microstrip Power Amplifier based on GaAs-FET for ISM Applications

2018 ◽  
Vol 8 (5) ◽  
pp. 3882
Author(s):  
Amine Rachakh ◽  
Larbi El Abdellaoui ◽  
Jamal Zbitou ◽  
Ahmed Errkik ◽  
Abdelali Tajmouati ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Return Loss ◽  
Maximum Output Power ◽  
Maximum Power ◽  
Design System ◽  
Stability Factor ◽  
Maximum Output ◽  
Power Gain ◽  
Microstrip Technology

Power Amplifiers (PA) are very indispensable components in the design of numerous types of communication transmitters employed in microwave technology. The methodology is exemplified through the design of a 2.45GHz microwave power Amplifier (PA) for the industrial, scientific and medical (ISM) applications using microstrip technology. The main design target is to get a maximum power gain while simultaneously achieving a maximum output power through presenting the optimum impedance which is characteristically carried out per adding a matching circuit between the source and the input of the power amplifier and between the load and the output of the power amplifier. A "T" matching technique is used at the input and the output sides of transistor for assure in band desired that this circuit without reflections and to obtain a maximum power gain. The proposed power amplifier for microwave ISM applications is designed, simulated and optimized by employing Advanced Design System (ADS) software by Agilent. The PA shows good performances in terms of return loss, output power, power gain and stability; the circuit has an input return loss of -38dB and an output return loss of -33.5dB. The 1-dB compression point is 8.69dBm and power gain of the PA is 19.4dBm. The Rollet's Stability measure B1 and the stability factor K of the amplifier is greater than 0 and 1 respectively, which shows that the circuit is unconditionally stable. The total chip size of the PA is 73.5× 36 mm2.

A 5.2/5.8 GHz Dual Band On-Off Keying Transmitter Design for Bio-Signal Transmission

2018 ◽  
Vol 3 (2) ◽  
Author(s):  
Chang-Hsi Wu ◽  
Hong-Cheng You ◽  
Shun-Zhao Huang
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Power Efficiency ◽  
Supply Voltage ◽  
Maximum Output Power ◽  
Dual Band ◽  
Maximum Output ◽  
Power Combiner ◽  
Power Added Efficiency ◽  
Chip Size

Abstract An architecture of 5.2/5.8-GHz dual-band on-off keying (DBOOK) modulated transmitter is designed in a 0.18-μm CMOS technology. The proposed DBOOK transmitter is used in the biosignal transmission system with high power efficiency and small area. To reduce power consumption and enhance output swing, two pairs of center-tapped transformers are used as both LC tank and source grounding choke for the designed voltage controlled oscillator (VCO). Switching capacitances are used to achieve dual band operations, and a complemented power combiner is used to merge the differential output power of VCO to a single-ended output. Besides, the linearizer circuits are used in the proposed power amplifier with wideband output matching to improve the linearity both at 5.2/5.8-GHz bands. The designed DBOOK transmitter is implemented by dividing it into two chips. One chip implements the dual-band switching VCO and power combiner, and the other chip implements a linear power amplifier including dual-band operation. The first chip drives an output power of 2.2mW with consuming power of 5.13 mW from 1.1 V supply voltage. With the chip size including pad of 0.61 × 0.91 m2, the measured data rate and transmission efficiency attained are 100 Mb/s and 51 pJ/bit, respectively. The second chip, for power enhanced mode, exhibits P1 dB of −9 dBm, IIP3 of 1 dBm, the output power 1 dB compression point of 12.42 dBm, OIP3 of about 21 dBm, maximum output power of 17.02/16.18 dBm, and power added efficiency of 17.13/16.95% for 5.2/ 5.8 GHz. The chip size including pads is 0:693 × 1:084mm2.

RF-MEMS multi-mode-matching networks for GaN power transistors

2014 ◽  
Vol 6 (5) ◽  
pp. 447-458 ◽  
Author(s):  
Sascha A. Figur ◽  
Friedbert van Raay ◽  
Rüdiger Quay ◽  
Larissa Vietzorreck ◽  
Volker Ziegler
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Rf Mems ◽  
Operation Mode ◽  
Maximum Output Power ◽  
Maximum Output ◽  
Mode Matching ◽  
Power Added Efficiency ◽  
Matching Networks ◽  
Multi Mode

This work presents radio-frequency-microelectromechanical-system (RF-MEMS)-based tunable input- and output-matching networks for a multi-band gallium nitride (GaN) power-amplifier applications. In the first part, circuit designs are shown and characterized for a fixed operation mode of the transistor, i.e. either a maximum-output-power- or a maximum-power-added-efficiency (PAE)-mode, which are finally combined into a multi-mode-matching network (M3N); the M3N allows to tune the operation mode of the transistor independently of its operational frequency. The matching networks are designed to provide optimum matching for the power amplifier at three to six different operating frequencies for maximum-output-power- and maximum-PAE-mode. In the frequency range from 3.5 to 8.5 GHz, return losses of 10 dB and higher were measured and insertion losses of 0.5–1.9 dB were demonstrated for the output-matching networks. Further characterizations were performed to test the dependency on the RF-input power, and no changes were observed up to power levels of 34 dBm when cold-switched.

A high gain and high linearity class-AB power amplifier for WCDMA applications

2013 ◽  
Vol 31 (1) ◽  
pp. 1-7
Author(s):  
Harikrishnan Ramiah ◽  
U. Eswaran ◽  
J. Kanesan
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Maximum Output Power ◽  
High Gain ◽  
Main Stage ◽  
Maximum Output ◽  
Gain Compression ◽  
Content Type ◽  
Fully Integrated ◽  
Class Ab

Purpose – The purpose of this paper is to design and realize a high gain power amplifier (PA) with low output back-off power using the InGaP/GaAs HBT process for WCDMA applications from 1.85 to 1.91 GHz. Design/methodology/approach – A three stages cascaded PA is designed which observes a high power gain. A 100 mA of quiescent current helps the PA to operate efficiently. The final stage device dimension has been selected diligently in order to deliver a high output power. The inter-stage match between the driver and main stage has been designed to provide maximum power transfer. The output matching network is constructed to deliver a high linear output power which meets the WCDMA adjacent channel leakage ratio (ACLR) requirement of −33 dBc close to the 1 dB gain compression point. Findings – With the cascaded topology, a maximum 31.3 dB of gain is achieved at 1.9 GHz. S11 of less than −18 dB is achieved across the operating frequency band. The maximum output power is indicated to be 32.7 dBm. An ACLR of −33 dBc is achieved at maximum linear output power of 31 dBm. Practical implications – The designed PA is an excellent candidate to be employed in the WCDMA transmitter chain without the aid of additional driver amplifier and linearization circuits. Originality/value – In this work, a fully integrated GaAs HBT PA has been implemented which is capable to operate linearly close to its 1 dB gain compression point.

A high gain 10 watts wideband distributed power amplifier for two way radio system

2018 ◽  
Vol 35 (1) ◽  
pp. 24-32
Author(s):  
Pragash Sangaran ◽  
Narendra Kumar ◽  
Jagadheswaran Rajendran ◽  
Andrei Grebennikov
Keyword(s):  
Power Amplifier ◽  
High Power ◽  
Design Methodology ◽  
Maximum Output Power ◽  
Maximum Output ◽  
Power Gain ◽  
Power Circuit ◽  
Radio System ◽  
Distributed Power ◽  
Content Type

Purpose This paper aims to propose a practical design methodology of high-power wideband power amplifier. Design/methodology/approach The distributed power amplification method is used for a Gallium Nitride device to achieve wideband operation. To achieve the high power without trading-off the bandwidth and gain, a methodology to extract the package-loading effect is proposed and verified. Findings A maximum output power of 10 W is achieved from 100 MHz to 2 GHz with a wideband power gain of 32 dB in measurement. This performance is achieved through a single section matching network. Research limitations/implications Measurement accuracy is dependable to the thermal behaviour of the high-power device. Practical implications The proposed technique is an excellent solution to be used in the two way radio power amplifier that minimizes the fundamental trade-off issue between power, gain, bandwidth and efficiency. Originality/value In this work, a practical distributed power amplifier (DPA) design methodology is proposed that reduces the development cycle time for industrial engineers working on high-power circuit design application.

DOUBLE SUPPLY, LINEAR, AND HIGH EFFICIENCY PUSH AMPLIFIER DESIGN FOR ENVELOPE TRACKING POWER AMPLIFIERS IN WiMAX APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450113 ◽  
Author(s):  
MOHAMMAD MOGHADDAM TABRIZI ◽  
NASSER MASOUMI
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
High Performance ◽  
High Efficiency ◽  
Maximum Output Power ◽  
Total Efficiency ◽  
Maximum Output ◽  
Error Vector Magnitude ◽  
Power Added Efficiency ◽  
Amplifier Design

In this work, a novel and efficient approach is proposed to optimize linearity and efficiency of a power amplifier used in mobile communication applications. A linear and high performance push amplifier is designed and analyzed to extract design equations for an optimum performance. The proposed push amplifier has two sections; an analog section and a switching section. The analog section provides the required linearity and the switching section guarantees the satisfaction of the total efficiency level. Double power supply scheme is used in push amplifiers to enhance its performance. Two separate power supplies are employed for linear and switching sections of push amplifiers which have different voltage levels. The implemented circuit is simulated using HSPICERF with TSMC models for active and passive elements. The proposed power amplifier (PA) provides a maximum output power of 25 dBm and power added efficiency (PAE) as high as 51% at 2.5 GHz operation frequency. At 1-dB compression point, this PA exhibits output power of 25 dBm with 48% PAE and 4.5% error vector magnitude (EVM) which is appropriate for 64QAM OFDM signals.

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