Low Power Current Mode Poly-Silicon TFT Digital Circuit Design Method for High Speed SOP Components

2007 ◽  
Author(s):  
J.-C. Lee ◽  
M.-P. Hong ◽  
J. Y. Jeong
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
High Speed ◽  
Design Method ◽  
Current Mode ◽  
Digital Circuit ◽  
Poly Silicon ◽  
Digital Circuit Design

scholarly journals Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style

2016 ◽  
Vol 2016 ◽  
pp. 1-10
Author(s):  
Neeta Pandey ◽  
Damini Garg ◽  
Kirti Gupta ◽  
Bharat Choudhary
Keyword(s):  
Circuit Design ◽  
High Speed ◽  
Current Mode ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Mixed Signal ◽  
Current Mode Logic ◽  
Digital Circuit Design ◽  
Pass Transistor ◽  
Logic Functions

This paper proposes hybrid dynamic current mode logic (H-DyCML) as an alternative to existing dynamic CML (DyCML) style for digital circuit design in mixed-signal applications. H-DyCML introduces complementary pass transistors for implementation of logic functions. This allows reduction in the stacked source-coupled transistor pair levels in comparison to the existing DyCML style. The resulting reduction in transistor pair levels permits significant speed improvement. SPICE simulations using TSMC 180 nm and 90 nm CMOS technology parameters are carried out to verify the functionality and to identify their advantages. Some issues related to the compatibility of the complementary pass transistor logic have been investigated and the appropriate solutions have been proposed. The performance of the proposed H-DyCML gates is compared with the existing DyCML gates. The comparison confirms that proposed H-DyCML gates is faster than the existing DyCML gates.

SINUSOIDAL CLOCKED SENSE-AMPLIFIER-BASED ENERGY RECOVERY FLIP-FLOPS

2014 ◽  
Vol 23 (05) ◽  
pp. 1450066
Author(s):  
JITENDRA KANUNGO ◽  
S. DASGUPTA
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Energy Recovery ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Sense Amplifier ◽  
Simulation Based ◽  
Digital Circuit Design

Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-amplifier based flip-flop (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-out at 90 nm CMOS technology node. The proposed flip-flop operating with energy recovery single phase sinusoidal clock shows better performance. The proposed flip-flop also reduces the leakage current and glitch.

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