A single tile in a mesh-based FPGA includes both the routing block and the logic
block. The area estimate of a tile in an FPGA is used to determine the physical
length of an FPGA’s routing segments. An estimate of the physical length of the
routing segments is needed in order to accurately assess the performance of a
proposed FPGA architecture. The VPR (Versatile Place and Route) and the
COFFE (Circuit Optimization for FPGA Exploration) tools are widely used meshbased FPGA exploration environments. These tools map, place, and route
benchmark circuits on FPGA architectures. Subsequently, based on area and delay
measurements, the best architectural parameters of an FPGA are decided. The area
models of the VPR and COFEE tools take only transistor size as input to estimate
the area of a circuit. Realistically, the layout area of a circuit depends on both the
transistor size and the number of metal layers that are available to route the circuit.
This work measures the effect of the number of metal layers that are available for
routing on FPGA layout area through a series of carefully laid out 4-LUTs (4-input
Lookup Tables). Based on measured results, a correction factor for the COFFE area equation is determined. The correction factor is a function of both the
transistor drive strength and the number of metal layers that are available for
routing. Consequently, a new area estimation equation, that is based on the
COFFE area model, is determined. The proposed area equation takes into
consideration the effect of both the transistor drive strength and the number of
metal layers that are available for routing on layout area. The area prediction error
of the proposed area equation is significantly less than the area prediction errors of
the VPR and COFFE area models.
Investigating The Efficiency Of The VPR And COFFE Area Models In Predicting The Layout Area Of FPGA Lookup Tables
