Multitoken-Based Power Management for NAND Flash Storage Devices

2020 ◽  
Vol 39 (10) ◽  
pp. 2898-2910
Author(s):  
Taehee You ◽  
Sangwoo Han ◽  
Young Min Park ◽  
Hyuk-Jun Lee ◽  
Eui-Young Chung
Keyword(s):  
Power Management ◽  
Nand Flash ◽  
Flash Storage ◽  
Storage Devices

scholarly journals Compression-Assisted Adaptive ECC and RAID Scattering for NAND Flash Storage Devices

Sensors ◽  
2020 ◽  
Vol 20 (10) ◽  
pp. 2952 ◽  
Author(s):  
Seung-Ho Lim ◽  
Ki-Woong Park
Keyword(s):  
Flash Memory ◽  
Error Recovery ◽  
Recovery Phase ◽  
Error Correction Codes ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Storage ◽  
Storage Devices ◽  
Complementary Method ◽  
Compressed Data

NAND flash memory-based storage devices are vulnerable to errors induced by NAND flash memory cells. Error-correction codes (ECCs) are integrated into the flash memory controller to correct errors in flash memory. However, since ECCs show inherent limits in checking the excessive increase in errors, a complementary method should be considered for the reliability of flash storage devices. In this paper, we propose a scheme based on lossless data compression that enhances the error recovery ability of flash storage devices, which applies to improve recovery capability both of inside and outside the page. Within a page, ECC encoding is realized on compressed data by the adaptive ECC module, which results in a reduced code rate. From the perspective of outside the page, the compressed data are not placed at the beginning of the page, but rather is placed at a specific location within the page, which makes it possible to skip certain pages during the recovery phase. As a result, the proposed scheme improves the uncorrectable bit error rate (UBER) of the legacy system.

scholarly journals A Crash Recovery Scheme for a Hybrid Mapping FTL in NAND Flash Storage Devices

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 327
Author(s):  
Jong-Hyeok Park ◽  
Dong-Joo Park ◽  
Tae-Sun Chung ◽  
Sang-Won Lee
Keyword(s):  
Flash Memory ◽  
Practical Importance ◽  
Normal Operation ◽  
Storage Device ◽  
Nand Flash ◽  
Hybrid Mapping ◽  
Flash Storage ◽  
Storage Devices ◽  
Recovery Scheme ◽  
Crash Recovery

An FTL (flash translation layer), which most flash storage devices are equipped with, needs to guarantee the consistency of modified metadata from a sudden power failure. This crash recovery scheme significantly affects the writing performance of a flash storage device during its normal operation, as well as its reliability and recovery performance; therefore, it is desirable to make the crash recovery scheme efficient. Despite the practical importance of a crash recovery scheme in an FTL, few works exist that deal with the crash recovery issue in FTL in a comprehensive manner. This study proposed a novel crash recovery scheme called FastCheck for a hybrid mapping FTL called Fully Associative Sector Translation (FAST). FastCheck can efficiently secure the newly generated address-mapping information using periodic checkpoints, and at the same time, leverages the characteristics of an FAST FTL, where the log blocks in a log area are used in a round-robin way. Thus, it provides two major advantages over the existing FTL recovery schemes: one is having a low logging overhead during normal operations in the FTL and the other to have a fast recovery time in an environment where the log provisioning rate is relatively high, e.g., over 20%, and the flash memory capacity is very large, e.g., 32 GB or 64 GB.

scholarly journals A Novel B-Tree Index with Cascade Memory Nodes for Improving Sequential Write Performance on Flash Storage Devices

2020 ◽  
Vol 10 (3) ◽  
pp. 747
Author(s):  
Bo-Kyeong Kim ◽  
Gun-Woo Kim ◽  
Dong-Ho Lee
Keyword(s):  
Flash Memory ◽  
High Reliability ◽  
Index Structure ◽  
Storage Device ◽  
Nand Flash ◽  
Solid State Drives ◽  
Flash Storage ◽  
Storage Devices ◽  
B Trees ◽  
Tree Index

Flash storage devices such as solid-state drives and multimedia cards have been widely used in various applications because of their fast access speed, low power consumption, and high reliability. They consist of NAND flash memories that perform slow block erasures before overwriting data on a prewritten page. This characteristic can lead to performance degradation when applying the original B-tree on the flash storage device without any changes. Although various B-trees have been proposed for flash memory, they still require many flash operations that degrade overall performance. To address the problem, we propose a novel B-tree index structure that reduces the number of write operations and improves the sequential writes by employing cascade memory nodes. The proposed B-tree index structure delays the updates for the modified B-tree nodes and later performs batch writes in a cascade manner. Also, when records with continuous key values are sequentially inserted, the proposed B-tree index structure does not split the leaf node so that it improves write throughput and page utilization. Through mathematical analysis and experimental results, we show that the proposed B-tree index structure always yields better performance than existing techniques.

VBBMS: A Novel Buffer Management Strategy for NAND Flash Storage Devices

2019 ◽  
Vol 65 (2) ◽  
pp. 134-141 ◽  
Author(s):  
Chenjie Du ◽  
Yingbiao Yao ◽  
Jie Zhou ◽  
Xiaorong Xu
Keyword(s):  
Management Strategy ◽  
Buffer Management ◽  
Nand Flash ◽  
Flash Storage ◽  
Storage Devices

A Design of High Speed Data Acquisition and Storage System

2013 ◽  
Vol 367 ◽  
pp. 541-543
Author(s):  
Yun Peng Li
Keyword(s):  
Speech Recognition ◽  
High Speed ◽  
Storage System ◽  
Nand Flash ◽  
Flash Storage ◽  
Reading And Writing ◽  
Hardware Development ◽  
High Speed Data Acquisition ◽  
High Speed Data ◽  
And Storage

This article focuses on research and implementation of a kind of solid storage system that is based on NAND flash which can store the data with high speed and huge capacity. A design with quad 1.25Gsps ADC and flash storage array with 1TB is demonstrated in the paper. The design is applied widely in many fields such as radar, communication and speech recognition. The detail of hardware development is also introduced in the thesis. In addition, a method is discussed to approve the reading and writing bandwidth by parallel operations on multiple pieces of flash. By using the method, the data bandwidth is arrived 6GB/S.

scholarly journals Block Utilization-Aware Buffer Replacement Scheme for Mobile NAND Flash Storage

2014 ◽  
Vol E97.D (9) ◽  
pp. 2510-2513 ◽  
Author(s):  
Dong Hyun KANG ◽  
Changwoo MIN ◽  
Young Ik EOM
Keyword(s):  
Nand Flash ◽  
Flash Storage ◽  
Replacement Scheme

Design and Realization of NAND Flash Based on Embedded Linux System

2011 ◽  
Vol 219-220 ◽  
pp. 972-975 ◽  
Author(s):  
Zhi Jian Yin ◽  
Yun Fei He ◽  
Chun Ru Xiong ◽  
Run Yang Zhong
Keyword(s):  
File System ◽  
Embedded Linux ◽  
Nand Flash ◽  
Innovative Design ◽  
Flash Storage ◽  
Embedded Linux System

This paper utilizes ARM 9 series chips such as S3C2440 as the CPU to realize an embedded Linux system. Due to the integration of NAND Flash in S3C2440, it is easy to connect the NAND Flash external devices in the perspective of hardware. After that, the system combines the serial ports which intend to load and debug the driver of NAND Flash, realizing the loading and uninstalling of NAND Flash storage modules. The innovative design and realization is a basic for the implementation of YAFFS file system in the Linux terminals.

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