A Crash Recovery Scheme for a Hybrid Mapping FTL in NAND Flash Storage Devices

An FTL (flash translation layer), which most flash storage devices are equipped with, needs to guarantee the consistency of modified metadata from a sudden power failure. This crash recovery scheme significantly affects the writing performance of a flash storage device during its normal operation, as well as its reliability and recovery performance; therefore, it is desirable to make the crash recovery scheme efficient. Despite the practical importance of a crash recovery scheme in an FTL, few works exist that deal with the crash recovery issue in FTL in a comprehensive manner. This study proposed a novel crash recovery scheme called FastCheck for a hybrid mapping FTL called Fully Associative Sector Translation (FAST). FastCheck can efficiently secure the newly generated address-mapping information using periodic checkpoints, and at the same time, leverages the characteristics of an FAST FTL, where the log blocks in a log area are used in a round-robin way. Thus, it provides two major advantages over the existing FTL recovery schemes: one is having a low logging overhead during normal operations in the FTL and the other to have a fast recovery time in an environment where the log provisioning rate is relatively high, e.g., over 20%, and the flash memory capacity is very large, e.g., 32 GB or 64 GB.

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A Novel B-Tree Index with Cascade Memory Nodes for Improving Sequential Write Performance on Flash Storage Devices

Applied Sciences ◽

10.3390/app10030747 ◽

2020 ◽

Vol 10 (3) ◽

pp. 747

Author(s):

Bo-Kyeong Kim ◽

Gun-Woo Kim ◽

Dong-Ho Lee

Keyword(s):

Flash Memory ◽

High Reliability ◽

Index Structure ◽

Storage Device ◽

Nand Flash ◽

Solid State Drives ◽

Flash Storage ◽

Storage Devices ◽

B Trees ◽

Tree Index

Flash storage devices such as solid-state drives and multimedia cards have been widely used in various applications because of their fast access speed, low power consumption, and high reliability. They consist of NAND flash memories that perform slow block erasures before overwriting data on a prewritten page. This characteristic can lead to performance degradation when applying the original B-tree on the flash storage device without any changes. Although various B-trees have been proposed for flash memory, they still require many flash operations that degrade overall performance. To address the problem, we propose a novel B-tree index structure that reduces the number of write operations and improves the sequential writes by employing cascade memory nodes. The proposed B-tree index structure delays the updates for the modified B-tree nodes and later performs batch writes in a cascade manner. Also, when records with continuous key values are sequentially inserted, the proposed B-tree index structure does not split the leaf node so that it improves write throughput and page utilization. Through mathematical analysis and experimental results, we show that the proposed B-tree index structure always yields better performance than existing techniques.

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Compression-Assisted Adaptive ECC and RAID Scattering for NAND Flash Storage Devices

Sensors ◽

10.3390/s20102952 ◽

2020 ◽

Vol 20 (10) ◽

pp. 2952 ◽

Cited By ~ 1

Author(s):

Seung-Ho Lim ◽

Ki-Woong Park

Keyword(s):

Flash Memory ◽

Error Recovery ◽

Recovery Phase ◽

Error Correction Codes ◽

Nand Flash ◽

Nand Flash Memory ◽

Flash Storage ◽

Storage Devices ◽

Complementary Method ◽

Compressed Data

NAND flash memory-based storage devices are vulnerable to errors induced by NAND flash memory cells. Error-correction codes (ECCs) are integrated into the flash memory controller to correct errors in flash memory. However, since ECCs show inherent limits in checking the excessive increase in errors, a complementary method should be considered for the reliability of flash storage devices. In this paper, we propose a scheme based on lossless data compression that enhances the error recovery ability of flash storage devices, which applies to improve recovery capability both of inside and outside the page. Within a page, ECC encoding is realized on compressed data by the adaptive ECC module, which results in a reduced code rate. From the perspective of outside the page, the compressed data are not placed at the beginning of the page, but rather is placed at a specific location within the page, which makes it possible to skip certain pages during the recovery phase. As a result, the proposed scheme improves the uncorrectable bit error rate (UBER) of the legacy system.

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A High Temp standalone 4MByte Flash memory with SPI Interface for 210C applications

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/hitec-2012-tp11 ◽

2012 ◽

Vol 2012 (HITEC) ◽

pp. 000066-000071

Author(s):

Wade VonBergen ◽

Madhu Basude

Keyword(s):

Flash Memory ◽

Critical Parameters ◽

Storage Device ◽

Hole Drilling ◽

Data Logging ◽

Cell Array ◽

Flash Storage ◽

High Level ◽

Spi Interface

This paper covers the internal architecture, testability & performance characterization of Texas Instruments ™ High-Temp 210C 4MByte standalone Flash storage device. It will be available in a 14-pin ceramic dual Flat pack package as well as a Known Good Die (KGD) option. The device is manufactured in TI's 180nm 1.8V flash process with 3.3V IOs. The design implements 8 banks of flash organized into 2M × 16 bits surrounded by a SPI controller. The SPI controller interfaces asynchronously with an internal flash controller. The flash controller is clocked by FCLK, and controls the flash charge pump to access & operate the flash to program, read, erase, validate etc. The SPI controller is responsible for translating and executing the high level SPI protocol commands to the internal flash controller & its registers. A simple and flexible protocol was developed to access the flash array via the SPI supporting various commands and configuration capabilities. Testability of critical parameters for reliable 210C flash operation is ensured with the implementation of an internal test port accessible through a parallel interface (for TI Internal use only). The test port, and a SPI initiated BIST controller are used to provide full & comprehensive characterization of the flash bit cell array, as well as the flash-pump across temperature & frequencies. The form factor, size, and pin out of this flash device is primarily focused on data logging for narrow & space limited extreme harsh environments such as the down-hole drilling industry.

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Evaluating Encryption Algorithms for Sensitive Data Using Different Storage Devices

Scientific Programming ◽

10.1155/2020/6132312 ◽

2020 ◽

Vol 2020 ◽

pp. 1-9 ◽

Cited By ~ 1

Author(s):

Bahman A. Sassani (Sarrafpour) ◽

Mohammed Alkorbi ◽

Noreen Jamil ◽

M. Asif Naeem ◽

Farhaan Mirza

Keyword(s):

Flash Memory ◽

Full Range ◽

Data Encryption ◽

Storage Device ◽

Sensitive Data ◽

Hard Drives ◽

Storage Devices ◽

Aes Algorithm ◽

Encryption Algorithms ◽

Storage Encryption

Sensitive data need to be protected from being stolen and read by unauthorized persons regardless of whether the data are stored in hard drives, flash memory, laptops, desktops, and other storage devices. In an enterprise environment where sensitive data is stored on storage devices, such as financial or military data, encryption is used in the storage device to ensure data confidentiality. Nowadays, the SSD-based NAND storage devices are favored over HDD and SSHD to store data because they offer increased performance and reduced access latency to the client. In this paper, the performance of different symmetric encryption algorithms is evaluated on HDD, SSHD, and SSD-based NAND MLC flash memory using two different storage encryption software. Based on the experiments we carried out, Advanced Encryption Standard (AES) algorithm on HDD outperforms Serpent and Twofish algorithms in terms of random read speed and write speed (both sequentially and randomly), whereas Twofish algorithm is slightly faster than AES in sequential reading on SSHD and SSD-based NAND MLC flash memory. By conducting full range of evaluative tests across HDD, SSHD, and SSD, our experimental results can give better idea for the storage consumers to determine which kind of storage device and encryption algorithm is suitable for their purposes. This will give them an opportunity to continuously achieve the best performance of the storage device and secure their sensitive data.

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Flash-Aware Page Replacement Algorithm

Mathematical Problems in Engineering ◽

10.1155/2014/136246 ◽

2014 ◽

Vol 2014 ◽

pp. 1-11 ◽

Cited By ~ 2

Author(s):

Guangxia Xu ◽

Lingling Ren ◽

Yanbing Liu

Keyword(s):

Flash Memory ◽

Main Memory ◽

Consumer Electronics ◽

Storage Device ◽

Cost Ratio ◽

Nand Flash ◽

Nand Flash Memory ◽

Selection Scheme ◽

Replacement Algorithm ◽

Memory Resource

Due to the limited main memory resource of consumer electronics equipped with NAND flash memory as storage device, an efficient page replacement algorithm called FAPRA is proposed for NAND flash memory in the light of its inherent characteristics. FAPRA introduces an efficient victim page selection scheme taking into account the benefit-to-cost ratio for evicting each victim page candidate and the combined recency and frequency value, as well as the erase count of the block to which each page belongs. Since the dirty victim page often contains clean data that exist in both the main memory and the NAND flash memory based storage device, FAPRA only writes the dirty data within the victim page back to the NAND flash memory based storage device in order to reduce the redundant write operations. We conduct a series of trace-driven simulations and experimental results show that our proposed FAPRA algorithm outperforms the state-of-the-art algorithms in terms of page hit ratio, the number of write operations, runtime, and the degree of wear leveling.

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Probability-based static wear-leveling algorithm for block and hybrid-mapping NAND flash memory

Design Automation for Embedded Systems ◽

10.1007/s10617-013-9108-3 ◽

2012 ◽

Vol 16 (4) ◽

pp. 241-264 ◽

Cited By ~ 3

Author(s):

Yared Hailu Gudeta ◽

Se Jin Kwon ◽

Eun-Sun Cho ◽

Tae-Sun Chung

Keyword(s):

Flash Memory ◽

Nand Flash ◽

Hybrid Mapping ◽

Nand Flash Memory ◽

Wear Leveling

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Comparative Analysis Study on SSD, HDD, and SSHD

Turkish Journal of Computer and Mathematics Education (TURCOMAT) ◽

10.17762/turcomat.v12i3.1644 ◽

2021 ◽

Vol 12 (3) ◽

pp. 3635-3641

Author(s):

Ms.Hepisuthar Et.al

Keyword(s):

Flash Memory ◽

Nand Flash ◽

Nand Flash Memory ◽

Time Data ◽

Data Movement ◽

Storage Devices ◽

User Input ◽

Current Century ◽

Long Time ◽

Computing Speed

In the Current Century, permeant storage devices and methods of storing data changed from traditional HDD to SDD. In this document, we discuss the merge of HDD and SSD. The Abbreviation of SSHD is called the solid-state hybrid disk. A mixture of both secondary devices to enhance the performance of the system. Inside the SSD, data movement events occur without any user input. Recent research has suggested that SSD has only the Replacement of secondary storage. HDD is also good in life span with longer life. It’s more reliable for long time data contained in this. HDD storage has typical magnetic fields for store data. SSD contains NAND flash memory to write the data in the drive. Based on the method and material of storing different. HDD and SSD feature well to upgrade with technology in Computer filed. For enhancing computing speed and excellent processing SSHD good to use in computer.Ratio increase of SSHD usage in current laptop and in computer system.

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