Interactions Between Line Edge Roughness and Random Dopant Fluctuation in Nonplanar Field-Effect Transistor Variability

2013 ◽  
Vol 60 (10) ◽  
pp. 3277-3284 ◽  
Author(s):  
Greg Leung ◽  
Chi On Chui
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Line Edge Roughness ◽  
Random Dopant Fluctuation ◽  
Edge Roughness ◽  
Effect Transistor ◽  
Random Dopant

scholarly journals A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs

Materials ◽  
2019 ◽  
Vol 12 (15) ◽  
pp. 2391 ◽  
Author(s):  
Natalia Seoane ◽  
Daniel Nagy ◽  
Guillermo Indalecio ◽  
Gabriel Espiñeira ◽  
Karol Kalna ◽  
...  
Keyword(s):  
Field Effect Transistor ◽  
Three Dimensional ◽  
Gate Length ◽  
Line Edge Roughness ◽  
Voltage Standard ◽  
A Value ◽  
Edge Roughness ◽  
Effect Transistor ◽  
Study Performance ◽  
The Ideal

An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device exhibits an off-current (I OFF) of 0 . 03 μA/μm, and an on-current (I ON) of 1770 μA/μm, with the I ON / I OFF ratio 6 . 63 × 10 4, a value 27 % larger than that of a 10 . 7 nm gate length Si FinFET. The device SS is 71 mV/dec, no far from the ideal limit of 60 mV/dec. The threshold voltage standard deviation due to statistical combination of four sources of variability (line- and gate-edge roughness, metal grain granularity, and random dopants) is 55 . 5 mV, a value noticeably larger than that of the equivalent FinFET (30 mV). Finally, using a fluctuation sensitivity map, we establish which regions of the device are the most sensitive to the line-edge roughness and the metal grain granularity variability effects. The on-current of the device is strongly affected by any line-edge roughness taking place near the source-gate junction or by metal grains localised between the middle of the gate and the proximity of the gate-source junction.

scholarly journals Impact of Process-Induced Variations on Negative Capacitance Junctionless Nanowire FET

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1899
Author(s):  
Yejoo Choi ◽  
Jinwoong Lee ◽  
Jaehyuk Lim ◽  
Seungjun Moon ◽  
Changhwan Shin
Keyword(s):  
Work Function ◽  
Device Performance ◽  
Negative Capacitance ◽  
Line Edge Roughness ◽  
Random Dopant Fluctuation ◽  
Edge Roughness ◽  
The Impact ◽  
Random Dopant

In this study, the impact of the negative capacitance (NC) effect on process-induced variations, such as work function variation (WFV), random dopant fluctuation (RDF), and line edge roughness (LER), was investigated and compared to those of the baseline junctionless nanowire FET (JL-NWFET) in both linear (Vds = 0.05 V) and saturation (Vds = 0.5 V) modes. Sentaurus TCAD and MATLAB were used for the simulation of the baseline JL-NWFET and negative capacitance JL-NWFET (NC-JL-NWFET). Owing to the NC effect, the NC-JL-NWFET showed less variation in terms of device performance, such as σ[Vt], σ[SS], σ[Ion/Ioff], σ[Vt]/µ[Vt], σ[SS]/µ[SS], and σ[Ion/Ioff]/µ[Ion/Ioff], and enhanced device performance, which implies that the NC effect can successfully control the variation-induced degradation.

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