scholarly journals CORDIC Architectures: A Survey

VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-19 ◽  
Author(s):  
B. Lakshmi ◽  
A. S. Dhar

In the last decade, CORDIC algorithm has drawn wide attention from academia and industry for various applications such as DSP, biomedical signal processing, software defined radio, neural networks, and MIMO systems to mention just a few. It is an iterative algorithm, requiring simple shift and addition operations, for hardware realization of basic elementary functions. Since CORDIC is used as a building block in various single chip solutions, the critical aspects to be considered are high speed, low power, and low area, for achieving reasonable overall performance. In this paper, we first classify the CORDIC algorithm based on the number system and discuss its importance in the implementation of CORDIC algorithm. Then, we present systematic and comprehensive taxonomy of rotational CORDIC algorithms, which are subsequently discussed in depth. Special attention has been devoted to the higher radix and flat techniques proposed in the literature for reducing the latency. Finally, detailed comparison of various algorithms is presented, which can provide a first-order information to designers looking for either further improvement of performance or selection of rotational CORDIC for a specific application.

2014 ◽  
Vol 2014 ◽  
pp. 1-20
Author(s):  
Bodhisatwa Sadhu ◽  
Martin Sturm ◽  
Brian M. Sadler ◽  
Ramesh Harjani

This paper explores passive switched capacitor based RF receiver front ends for spectrum sensing. Wideband spectrum sensors remain the most challenging block in the software defined radio hardware design. The use of passive switched capacitors provides a very low power signal conditioning front end that enables parallel digitization and software control and cognitive capabilities in the digital domain. In this paper, existing architectures are reviewed followed by a discussion of high speed passive switched capacitor designs. A passive analog FFT front end design is presented as an example analog conditioning circuit. Design methodology, modeling, and optimization techniques are outlined. Measurements are presented demonstrating a 5 GHz broadband front end that consumes only 4 mW power.


2011 ◽  
Vol 110-116 ◽  
pp. 4739-4743
Author(s):  
Su Xu

In this paper, a remote mine-gas concentration real-time detecting system is realized, which is cored at the MSP430F247 single chip and the Siemens TC35GSM module. The author introduces the system structure, functional principle and specific implementation scheme in details. Besides, the real-time collection of gas concentration, high-speed and accurate analysis on the data, setting and exceeding standard alarm of gas concentration, remote date transportation and good human-computer interaction displaying function can be realized through the making and debugging of the prototype.


2012 ◽  
Vol 9 (3) ◽  
pp. 325-342 ◽  
Author(s):  
Negovan Stamenkovic ◽  
Vladica Stojanovic

In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set {2n+1,2n,2n-1}, which avoids 2n+1 modulus, is used to design FIR filter. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters.


Author(s):  
A. F. Chernyavsky ◽  
A. A. Kolyada ◽  
S. Yu. Protasenya

The article is devoted to the problem of creation of high-speed neural networks (NN) for calculation of interval-index characteristics of a minimally redundant modular code. The functional base of the proposed solution is an advanced class of neural networks of a final ring. These neural networks perform position-modular code transformations of scalable numbers using a modified reduction technology. A developed neural network has a uniform parallel structure, easy to implement and requires the time expenditures of the order (3[log2b]+ [log2k]+6tsum  close to the lower theoretical estimate. Here b and k is the average bit capacity and the number of modules respectively; t sum is the duration of the two-place operation of adding integers. The refusal from a normalization of the numbers of the modular code leads to a reduction of the required set of NN of the finite ring on the (k – 1) component. At the same time, the abnormal configuration of minimally redundant modular coding requires an average k-fold increase in the interval index module (relative to the rest of the bases of the modular number system). It leads to an adequate increase in hardware expenses on this module. Besides, the transition from normalized to unregulated coding reduces the level of homogeneity of the structure of the NN for calculating intervalindex characteristics. The possibility of reducing the structural complexity of the proposed NN by using abnormal intervalindex characteristics is investigated.


2018 ◽  
Vol 26 (4) ◽  
pp. 172-184
Author(s):  
Muthna Jasim Fadhil

In modern systems communication, different methods have been improved to change the prior imitative techniques that process communication data with high speed. It is necessary to improve (OFDM) Orthogonal Frequency Division Multiplexing technique because the development in the guideline communication of wireless system which include security data and transmission data reliability. The applications communications of wireless is important to develop in order to optimize the process of communication leads to reduce the level consumption energy of the output level signal. The architecture of VLSI is used to optimize the performance transceiver in 802.11 n OFDM-MIMO systems, this idea concentrate on the design of 6x6 MIMO_OFDM system in software simulink of MATLAB then using generator system for transfer to code of VHDL and applying in FPGA Xilinx Spartan 3 XC3S200 . The modelsim used to get the simulation while Xilinx power estimator is used to calculate power. The results registered total power consumption about 94mW while compared with previous work  was 136mW which means a high reduction of about 30.8% .


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