Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology

Abstract The influence of temperature on single-event transient (SET) pulse width has always been a hot issue in the field of anti-irradiation. Based on 3D-TCAD simulation, the temperature sensitivity of the SET pulse width of 28-nm bulk devices has been studied. The simulation results show that the electrical characteristics of the device shows an anti-temperature effect, but the worst case of SET pulse width still occurs at high temperature rather than low temperature. The influence of the triple-well structure on the temperature sensitivity of the SET pulse width has also been studied. The N+ deep well can significantly increase the SET pulse width when hitting NMOS device and enhance the temperature sensitivity of the SET pulse width. The research content of this article will provide reference for the design of radiation resistant chip.

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Single event transient pulse width measurements in a 65-nm bulk CMOS technology at elevated temperatures

2010 IEEE International Reliability Physics Symposium ◽

10.1109/irps.2010.5488736 ◽

2010 ◽

Cited By ~ 9

Author(s):

M. J. Gadlage ◽

J. R. Ahlbin ◽

B. L. Bhuva ◽

L. W. Massengill ◽

R. D. Schrimpf

Keyword(s):

Pulse Width ◽

Elevated Temperatures ◽

Cmos Technology ◽

Single Event ◽

Single Event Transient ◽

Width Measurements

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The effect of elevated temperature on digital single event transient pulse widths in a bulk CMOS technology

2009 IEEE International Reliability Physics Symposium ◽

10.1109/irps.2009.5173246 ◽

2009 ◽

Cited By ~ 11

Author(s):

M. J. Gadlage ◽

J. R. Ahlbin ◽

B. Narasimham ◽

V. Ramachandran ◽

C. A. Dinkins ◽

...

Keyword(s):

Elevated Temperature ◽

Cmos Technology ◽

Single Event ◽

Single Event Transient

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Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

Electronics ◽

10.3390/electronics9010027 ◽

2019 ◽

Vol 9 (1) ◽

pp. 27

Author(s):

Jingtian Liu ◽

Qian Sun ◽

Bin Liang ◽

Jianjun Chen ◽

Yaqing Chi ◽

...

Keyword(s):

Circuit Design ◽

Analog Circuits ◽

Analog Circuit ◽

Forward Bias ◽

Cmos Technology ◽

Common Source ◽

Single Event ◽

Single Event Transient ◽

Body Effect ◽

Radiation Hardened

In analog circuit design, the bulks of MOSFETs can be tied to their respective sources to remove body effect. This paper models and analyzes the sensitivity of single-event transients (SETs) in common source (CS) amplifier with bulk tied to source (BTS) in 40 nm twin-well bulk CMOS technology. The simulation results present that the proposed BTS radiation-hardened-by-design (RHBD) technique can reduce charge collection and suppress the SET induced perturbation effectively in various input conditions of the circuit. The detailed analysis shows that the mitigation of SET is primarily due to the forward-bias of bulk potential. This technique is universally applicable in radiation-hardening design for analog circuits with negligible penalty.

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