Double-gate SOI devices for low-power and high-performance applications

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) ◽

10.1109/vlsid.2006.74 ◽

2006 ◽

Cited By ~ 6

Author(s):

K. Roy ◽

H. Mahmoodi ◽

S. Mukhopadhyay ◽

H. Ananthan ◽

A. Bansal ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

Double Gate ◽

Soi Devices

Double-gate SOI devices for low-power and high-performance applications

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005. ◽

10.1109/iccad.2005.1560067 ◽

2005 ◽

Cited By ~ 14

Author(s):

K. Roy ◽

H. Mahmoodi ◽

S. Mukhopadhyay ◽

H. Ananthan ◽

A. Bansal ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

Double Gate ◽

Soi Devices

Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581) ◽

10.1145/383082.383136 ◽

2001 ◽

Cited By ~ 7

Author(s):

Rongtian Zhang ◽

Kaushik Roy ◽

David Janes

Keyword(s):

Low Power ◽

Circuit Design ◽

High Performance ◽

Double Gate ◽

Fully Depleted ◽

Nano Scale

A low power four transistor Schmitt Trigger for asymmetric double gate fully depleted SOI devices

2003 IEEE International Conference on Robotics and Automation (Cat No 03CH37422) SOI-03) ◽

10.1109/soi.2003.1242882 ◽

2003 ◽

Cited By ~ 18

Author(s):

Cakici ◽

Bansal ◽

Roy

Keyword(s):

Low Power ◽

Schmitt Trigger ◽

Double Gate ◽

Fully Depleted ◽

Soi Devices

Low-Power High-Performance Asymmetrical Double-Gate Circuits Using Back-Gate-Controlled Wide-Tunable-Range Diode Voltage

IEEE Transactions on Electron Devices ◽

10.1109/ted.2007.902693 ◽

2007 ◽

Vol 54 (9) ◽

pp. 2263-2268 ◽

Cited By ~ 3

Author(s):

Keunwoo Kim ◽

Ching-Te Chuang ◽

J.B. Kuang ◽

H.C. Ngo ◽

K.J. Nowka

Keyword(s):

Low Power ◽

High Performance ◽

Double Gate ◽

Back Gate ◽

Tunable Range ◽

Diode Voltage

Novel high-density low-power high-performance double-gate logic techniques

2004 IEEE International SOI Conference (IEEE Cat No 04CH37573) SOI-04 ◽

10.1109/soi.2004.1391583 ◽

2005 ◽

Cited By ~ 6

Author(s):

Meng-Hsueh Chiang ◽

Keunwoo Kim ◽

C. Tretz ◽

Ching-Te Chuang

Keyword(s):

Low Power ◽

High Performance ◽

High Density ◽

Double Gate

High performance and low power domino logic using independent gate control in double-gate SOI MOSFETs

2004 IEEE International SOI Conference (IEEE Cat No 04CH37573) SOI-04 ◽

10.1109/soi.2004.1391558 ◽

2005 ◽

Cited By ~ 19

Author(s):

H. Mahmoodi ◽

S. Mukhopadhyay ◽

K. Roy

Keyword(s):

Low Power ◽

High Performance ◽

Double Gate ◽

Domino Logic ◽

Gate Control ◽

Independent Gate

Low-power high-performance double-gate fully depleted SOI circuit design

IEEE Transactions on Electron Devices ◽

10.1109/16.998595 ◽

2002 ◽

Vol 49 (5) ◽

pp. 852-862 ◽

Cited By ~ 22

Author(s):

Rongtian Zhang ◽

K. Roy

Keyword(s):

Low Power ◽

Circuit Design ◽

High Performance ◽

Double Gate ◽

Fully Depleted

To study high performance analysis of surround gate SOI MOSFET

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.8.10405 ◽

2018 ◽

Vol 7 (2.8) ◽

pp. 191

Author(s):

Arjimand Ashaf ◽

Manisha Tyagi ◽

Prashant Mani

Keyword(s):

Performance Analysis ◽

High Performance ◽

Device Modeling ◽

Double Gate ◽

Electrical Characteristics ◽

Soi Mosfet ◽

Gate Structure ◽

Rigorous Study ◽

Soi Devices

In this paper, we are presenting a rigorous study about SOI MOSFET devices development. The development of SOI devices based on gate structure from single gate to surround gate is presented in this paper. We compared the various electrical characteristics between Single gate, double gate, and bulk and also discussed the device modeling based on surround gate structure.

Double gate dynamic threshold voltage (DGDT) SOI MOSFETs for low power high performance designs

1997 IEEE International SOI Conference Proceedings ◽

10.1109/soi.1997.634943 ◽

2002 ◽

Cited By ~ 12

Author(s):

Liqiong Wei ◽

Zhanping Chen ◽

K. Roy

Keyword(s):

Low Power ◽

Threshold Voltage ◽

High Performance ◽

Dynamic Threshold ◽

Double Gate

Design high performance and low power 10T full adder cell using double gate MOSFET at 45nm technology

2013 International Conference on Control, Computing, Communication and Materials (ICCCCM) ◽

10.1109/iccccm.2013.6648903 ◽

2013 ◽

Cited By ~ 3

Author(s):

Anuj Kumar Shrivastava ◽

Shyam Akashe

Keyword(s):

Low Power ◽

High Performance ◽

Full Adder ◽

Double Gate ◽

Double Gate Mosfet