Highly porous interlayer dielectric for interconnect capacitance reduction

AbstractFuture interlayer dielectric (ILD) requirements necessitate reductions in dielectric constant to 2.1 within four years. Due to gaseous-like transport properties and near liquid-like densities, supercritical methods have been developed to dry and strip resist from these highly porous materials. Although a non-polar molecule, the solvating capability of supercritical CO2 (SCCO2) can be tailored by varying pressure, temperature, and co-solvents. This flexibility has been employed to remove photoresist and moisture from porous low-k films. The results of these experiments have been characterized using FTIR, ellipsometry, and SEM.

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Use of fractals to describe microstructures of porous thick-film platinum electrodes

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100121971 ◽

1992 ◽

Vol 50 (1) ◽

pp. 314-315

Author(s):

Steven D. Toteda

Keyword(s):

Fractal Dimension ◽

Power Plants ◽

Electrical Response ◽

Cubic Phase ◽

Platinum Electrodes ◽

Fine Grained ◽

Impedance Response ◽

Platinum Particles ◽

Energy Surfaces ◽

Highly Porous

Zirconia oxygen sensors, in such applications as power plants and automobiles, generally utilize platinum electrodes for the catalytic reaction of dissociating O2 at the surface. The microstructure of the platinum electrode defines the resulting electrical response. The electrode must be porous enough to allow the oxygen to reach the zirconia surface while still remaining electrically continuous. At low sintering temperatures, the platinum is highly porous and fine grained. The platinum particles sinter together as the firing temperatures are increased. As the sintering temperatures are raised even further, the surface of the platinum begins to facet with lower energy surfaces. These microstructural changes can be seen in Figures 1 and 2, but the goal of the work is to characterize the microstructure by its fractal dimension and then relate the fractal dimension to the electrical response. The sensors were fabricated from zirconia powder stabilized in the cubic phase with 8 mol% percent yttria. Each substrate was sintered for 14 hours at 1200°C. The resulting zirconia pellets, 13mm in diameter and 2mm in thickness, were roughly 97 to 98 percent of theoretical density. The Engelhard #6082 platinum paste was applied to the zirconia disks after they were mechanically polished ( diamond). The electrodes were then sintered at temperatures ranging from 600°C to 1000°C. Each sensor was tested to determine the impedance response from 1Hz to 5,000Hz. These frequencies correspond to the electrode at the test temperature of 600°C.

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Microstructural observations of the “Wustite-Spinel” coexistence following quenching of cation-excess spinels, Ni2(1+x)Ti1-xO4

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100178422 ◽

1990 ◽

Vol 48 (4) ◽

pp. 1058-1059

Author(s):

Ian M. Anderson ◽

Arnulf Muan ◽

C. Barry Carter

Keyword(s):

Film Growth ◽

Spinel Phase ◽

Model Systems ◽

Ion Milling ◽

Coexistence Of Phases ◽

Nonequilibrium Conditions ◽

Diffraction Patterns ◽

Spinel Structures ◽

Highly Porous ◽

Standard Techniques

Oxide mixtures which feature a coexistence of phases with the wüstite and spinel structures are considered model systems for the study of solid-state reaction kinetics, phase boundaries, and thin-film growth, and such systems are especially suited to TEM studies. (In this paper, the terms “wüstite” and “spinel” will refer to phases of those structure types.) The study of wüstite-spinel coexistence has been limited mostly to systems near their equilibrium condition, where the assumptions of local thermodynamic equilibrium are valid. The cation-excess spinels of the type Ni2(1+x)Ti1-xO4, which reportedly exist only above 1375°C4, provide an excellent system for the study of wüstite-spinel coexistence under highly nonequilibrium conditions. The nature of these compounds has been debated in the literature. X-ray and neutron powder diffraction patterns have been used to advocate the existence of a single-phase, non- stoichiometric spinel. TEM studies of the microstructure have been used to suggest equilibrium coexistence of a stoichiometric spinel, Ni2TiO4, and a wüstite phase; this latter study has shown a coexistence of wüstite and spinel phases in specimens thought to have been composed of a single, non- stoichiometric spinel phase. The microstructure and nature of this phase coexistence is the focus of this study. Specimens were prepared by ball-milling a mixture of NiO and TiO2 powders with 10 wt.% TiO2. The mixture was fired in air at 1483°C for 5 days, and then quenched to room temperature. The aggregate thus produced was highly porous, and needed to be infiltrated prior to TEM sample preparation, which was performed using the standard techniques of lapping, dimpling, and ion milling.

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Packing Design of Carbon Layers in Kemerit Highly Porous Carbon Material

Химия в интересах устойчивого развития ◽

10.15372/khur20170613 ◽

2017 ◽

Keyword(s):

Porous Carbon ◽

Carbon Material ◽

Porous Carbon Material ◽

Packing Design ◽

Highly Porous

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Air Bridge Technology: A Comparison of Novel Interconnect Materials and Integration Schemes for Beyond 45 nm

MRS Proceedings ◽

10.1557/proc-766-e5.3 ◽

2003 ◽

Vol 766 ◽

Author(s):

Kenneth Foster ◽

Joost Waeterloos ◽

Don Frye ◽

Steve Froelicher ◽

Mike Mills

Keyword(s):

Dielectric Constants ◽

Advanced Technology ◽

Effective Dielectric Constant ◽

Device Performance ◽

Interlayer Dielectric ◽

Integration Schemes ◽

Stepwise Reduction ◽

Bridge Technology ◽

Integrated Device ◽

Compare And Contrast

AbstractThe electronics industry, in a continual drive for improved integrated device performance, is seeking increasingly lower dielectric constants (k) of the insulators that are used as interlayer dielectric (ILD) for advanced logic interconnects. As the industry continually seeks a stepwise reduction of the “effective” dielectric constant (keff), simple extendibility, leads to the consideration of the highest performance possible, namely air bridge technology. In this paper we will discuss requirements, integration schemes and properties for a novel class of materials that has been developed as part of an advanced technology probe into air bridge architecture. We will compare and contrast these potential technology offerings with other existing dense and porous ILD integration options, and show that the choice is neither trivial nor obvious.

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Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽

10.1557/s0883769400034151 ◽

1997 ◽

Vol 22 (10) ◽

pp. 19-27 ◽

Cited By ~ 86

Author(s):

Wei William Lee ◽

Paul S. Ho

Keyword(s):

Packing Density ◽

Propagation Delay ◽

Single Chip ◽

Crosstalk Noise ◽

Metal Line ◽

Total Delay ◽

Interlayer Dielectric ◽

Low Dielectric ◽

Interconnect Delay ◽

Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

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