Three-dimensional simulation of complex semiconductor device structures

Author(s):  
J. Burgler ◽  
P. Conti ◽  
G. Heiser ◽  
S. Paschedag ◽  
W. Fichtner
MRS Bulletin ◽  
2009 ◽  
Vol 34 (10) ◽  
pp. 738-743 ◽  
Author(s):  
Lincoln J. Lauhon ◽  
Praneet Adusumilli ◽  
Paul Ronsheim ◽  
Philip L. Flaitz ◽  
Dan Lawrence

AbstractThe development of laser-assisted atom-probe tomography (APT) analysis and new sample preparation approaches have led to significant advances in the characterization of semiconductor materials and device structures by APT. The high chemical sensitivity and three-dimensional spatial resolution of APT makes it uniquely capable of addressing challenges resulting from the continued shrinking of semiconductor device dimensions, the integration of new materials and interfaces, and the optimization of evolving fabrication processes. Particularly pressing concerns include the variability in device performance due to discrete impurity atom distributions, the phase and interface stability in contacts and gate dielectrics, and the validation of simulations of impurity diffusion. This overview of APT of semiconductors features research on metal-silicide contact formation and phase control, silicon field-effect transistors, and silicon and germanium nanowires. Work on silicide contacts to silicon is reviewed to demonstrate impurity characterization in small volumes and indicate how APT can facilitate defect mitigation and process optimization. Impurity contour analysis of a pFET semiconductor demonstrates the site-specificity that is achievable with current APTs and highlights complex device challenges that can be uniquely addressed. Finally, research on semiconducting nanowires and nanowire heterostructures demonstrates the potential for analysis of materials derived from bottom-up synthesis methods.


Author(s):  
James J. Demarest

Abstract With the 14nm technology node becoming a reality at today's state-of-the-art semiconductor manufacturing plants and the 10nm node actively being planned for, device structures have shrunk well beyond the minimum conventional transmission electron microscope (TEM) sample thickness: 50-100nm. This paper addresses the challenges in TEM sample preparation of sub 22nm three-dimensional test structures. As semiconductor device technology continues to shrink and become more complicated with the addition of three-dimensional device integration, unique sample preparation challenges will continue to arise. This opens the door to novel solutions for these problems like the one presented in this paper: an issue that arose where TEM projection effects interfered with proper characterization of a finFET test structure.


Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions


2008 ◽  
Vol 128 (2) ◽  
pp. 459-466 ◽  
Author(s):  
Yoshitaka Inui ◽  
Tadashi Tanaka ◽  
Tomoyoshi Kanno

2009 ◽  
Vol 19 (1) ◽  
pp. 75-90 ◽  
Author(s):  
Hong-Bing Xiong ◽  
Jian-Zhong Lin ◽  
Ze-Fei Zhu

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