Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

Processing and Properties of Cw Laser-Recrystallized Silicon Films on Amorphous Substrates

1980 ◽  
Vol 1 ◽  
Author(s):  
N. M. Johnson ◽  
D. K. Biegelsen ◽  
M. D. Moyer
Keyword(s):  
Thin Films ◽  
Semiconductor Device ◽  
Field Effect Transistors ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Control Surface ◽  
Crystal Silicon ◽  
Cw Laser ◽  
Laser Recrystallization

ABSTRACTCW laser recrystallization has been used to process silicon thin films as an integral step in semiconductor device fabrication. On continuous films of polycrystalline silicon, a silicon-nitride encapsulant is used to control surface morphology during laser recrystallization. For thin films on bulk glass substrates it is necessary to pattern the silicon layer in order to minimize microcracking as well as to control recrystallization. Over single crystal silicon substrates, test devices have been fabricated in silicon islands on dual-dielectric layers. Materials and device evaluation included TEM, current-voltage, capacitance-voltage, and EBIC measurements, and the test devices consisted of p-n junction diodes, MOS capacitors, and MOS field-effect transistors.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

Mapping of Process-Induced Dopant Redistributions by Electron Holography

2004 ◽  
Vol 10 (4) ◽  
pp. 462-469 ◽  
Author(s):  
Wolf-Dieter Rau ◽  
Alexander Orchowski
Keyword(s):  
Semiconductor Device ◽  
Device Fabrication ◽  
Electron Holography ◽  
Dopant Diffusion ◽  
Fundamental Parameters ◽  
Device Processing ◽  
Device Structures ◽  
Before And After ◽  
Potential Applications ◽  
Junction Potential

We present and review dopant mapping examples in semiconductor device structures by electron holography and outline their potential applications for experimental investigation of two-dimensional (2D) dopant diffusion on the nanometer scale. We address the technical challenges of the method when applied to transistor structures with respect to quantification of the results in terms of the 2Dp–njunction potential and critically review experimental boundary conditions, accuracy, and potential pitfalls. By obtaining maps of the inner electrostatic potential before and after anneals typically used in device processing, we demonstrate how the “vertical” and “lateral” redistribution of boron during device fabrication can directly be revealed. Such data can be compared with the results of process simulation to extract the fundamental parameters for dopant diffusion in complex device structures.

ChemInform Abstract: Growth of Buried Oxide Layers of Silicon-on-Insulator (SOI) Structures by Thermal Oxidation of the Top Silicon Layer.

ChemInform ◽  
2010 ◽  
Vol 28 (43) ◽  
pp. no-no
Author(s):  
E. SCHROER ◽  
S. HOPFE ◽  
Q. Y. TONG ◽  
U. GOESELE ◽  
W. SKORUPA
Keyword(s):  
Thermal Oxidation ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Oxide Layers ◽  
Buried Oxide

Diffusion of Silicon Interstitials in thin Silicon Films on Insulator in Neutral and Oxidising Annealing Ambients

1997 ◽  
Vol 469 ◽  
Author(s):  
Guénolé C.M. Silvestre
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Annealing Treatment ◽  
Silicon On Insulator ◽  
Buried Oxide ◽  
Thermal Oxide ◽  
Good Crystalline Quality ◽  
Thin Silicon ◽  
Experimental Values ◽  
Fault Growth

ABSTRACTSilicon-On-Insulator (SOI) materials have emerged as a very promising technology for the fabrication of high performance integrated circuits since they offer significant improvement to device performance. Thin silicon layers of good crystalline quality are now widely available on buried oxide layers of various thicknesses with good insulating properties. However, the SOI structure is quite different from that of bulk silicon. This paper will discuss a study of point-defect diffusion and recombination in thin silicon layers during high temperature annealing treatment through the investigation of stacking-fault growth kinetics. The use of capping layers such as nitride, thin thermal oxide and thick deposited oxide outlines the diffusion mechanisms of interstitials in the SOI structure. It also shows that the buried oxide layer is a very good barrier to the diffusion of point defects and that excess silicon interstitials may be reincorporated at the top interface with the thermal oxide through the formation of SiO species. Finally, from the experimental values of the activation energies for the growth and the shrinkage of stacking-faults, the energy of interstitial creation is evaluated to be 2.6 eV, the energy for interstitial migration to be 1.8 eV and the energy of interstitial generation during oxidation to be 0.2 eV.

Analysis Of Sige Fet Device Structures On Silicon-on-sapphire Substrates by X-Ray Diffraction

1998 ◽  
Vol 533 ◽  
Author(s):  
P. M. Mooney ◽  
J. O. Chu ◽  
J. A. Ott ◽  
J. L. Jordan-Sweet ◽  
B. S. Meyerson ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
High Vacuum ◽  
Chemical Vapor ◽  
Device Fabrication ◽  
Ultra High Vacuum ◽  
X Ray Diffraction ◽  
X Ray ◽  
Sapphire Substrates ◽  
Wafer Cleaning ◽  
Device Structures

AbstractSi/Si1-xGex, heterostructures on improved silicon-on-sapphire substrates were grown epitaxially by ultra-high vacuum chemical vapor deposition for application as p-channel field effect transistors. High-resolution triple-axis x-ray diffraction was used to analyze these structures quantitatively and to evaluate the effects of device fabrication processes on them. Out-;diffusion of Ge from the Si1-xGex, quantum well was observed after fabrication as was the change in thickness of the Si cap layer due to wafer cleaning and gate oxidation at 875 °C

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