Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies

2004 ◽  
Vol 127 (2) ◽  
pp. 120-126 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Flip Chip ◽  
Solder Joints ◽  
Numerical Study ◽  
Void Formation ◽  
Middle Layer ◽  
Molten Solder ◽  
Previous Theory ◽  
Solder Interconnects ◽  
Heating Profiles ◽  
High Lead

Understanding the formation of voids in solder joints is important for predicting the long-term reliability of solder interconnects. This paper reports experimental research on the formation of void bubbles within molten solder bumps in flip-chip connections. For flip-chip-soldered electronic components, which have small solder volume, voids can be more detrimental to reliability. A previous theory based on thermocapillary flow reveals that the direction of heating influences void formation. Using different heating profiles, 480 solder joints of flip-chip assemblies were processed. A high-lead 90Pb∕8Sn∕2Ag solder was employed in the experiments. The solder samples were microsectioned to determine the actual size or diameter of the voids. A database on sizes and locations of voids was then constructed. More defective bumps, 80%, and higher void volume were found when the solder was melted from top (flip-chip side) to bottom (test board side). The observation on cases with melting direction from bottom to top had 40% defective bumps. The results show that a single big void is near the solder bump center with a few small voids near the edge. This supports the numerical study based on the thermocapillary theory. When the melting direction was reversed, many small voids appear near the edge. Big and middle-size voids tend to stay in the middle and outer regions from top towards middle layer of the bump. This experimental finding does not completely agree with the interpretation on the formation of voids by thermocapillary theory, however, the results do show that heat flux direction plays significant role in the formation and distribution of void bubbles in molten solder.

Experiments on Fluid Mechanics in Flip-Chip Solder Connections

2003 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Flip Chip ◽  
Experimental Finding ◽  
Numerical Study ◽  
Void Formation ◽  
Molten Solder ◽  
Bottom Edge ◽  
Solder Bumps ◽  
Solder Reflow ◽  
Heating Profiles ◽  
Bottom To Top

This experimental research studies the formation of void bubbles within molten solder bumps in flip-chip connections. A theory based on thermocapillary flow reveals that the direction of heating influences void formation. Twelve chip-bump substrate assemblies were investigated using different heating profiles. A database on sizes and locations of voids in solder bumps was constructed. The observation on cases with melting direction from bottom to top supports the numerical study based on thermocapillary theory. The results show that a single big void is near the bump center with a few small voids near the edge when the melting direction is from bottom to top during solder reflow. When the melting direction was reversed, many small voids appear near the bottom edge with big voids in the middle of the bump. This experimental finding does not completely agree with the interpretation on the formation of voids by thermocapillary theory. However, the results do show that heat flux direction plays significant role in the formation and distribution of void bubbles in molten solder.

Study of void formation due to electromigration in flip-chip solder joints using Kelvin bump probes

2006 ◽  
Vol 89 (3) ◽  
pp. 032103 ◽  
Author(s):  
Y. W. Chang ◽  
S. W. Liang ◽  
Chih Chen
Keyword(s):  
Flip Chip ◽  
Solder Joints ◽  
Void Formation

Experimental Study of Void Formation in Eutectic and Lead-Free Solder Bumps of Flip-Chip Assemblies

2005 ◽  
Vol 128 (3) ◽  
pp. 202-207 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Experimental Study ◽  
Heat Flux ◽  
Flip Chip ◽  
Void Formation ◽  
Lead Free ◽  
Void Volume ◽  
Lead Free Solder ◽  
Solder Bumps ◽  
Free Solder ◽  
High Lead

This paper reports the experimental findings of void formation in eutectic and lead-free solder joints of flip-chip assemblies. A previous theory indicated that the formation of voids is determined by the direction of heating. The experiments were designed to examine the size and location of voids in the solder samples subject to different heat flux directions. A lead-free solder (Sn-3.5Ag-0.75Cu) and a eutectic solder (63Sn37Pb) were employed in the experiments. Previous experiments [Wang, D., and Panton, R. L., 2005, “Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies,” ASME J. Electron. Packag., 127(2), pp. 120–126; 2005, “Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps,” ASME J. Electron. Packag., 127(4), pp. 440–445] employed a high lead solder. 288 solder bumps were processed for each solder. Both eutectic and lead-free solder have shown fewer voids and much smaller void volume than those for high-lead solder. Compared with lead-free solder, eutectic solder has a slightly lower void volume and a lower percentage of defective bumps. For both eutectic and lead-free solders, irrespective of the cooling direction, heating solder samples from the top shows fewer defective bumps and smaller void volume. No significant effect on void formation for either eutectic or lead-free solder was found via reversing the heat flux direction during cooling. Unlike high-lead solder, small voids in eutectic or lead-free solder comprised 35-88% of the total void volume. The final distribution of voids shows a moderate agreement with thermocapillary theory, indicating the significance of the temperature gradient on the formation of voids.

Numerical Simulations of Electromigration and Stress Migration Driven Void Propagation in Pb Free Solder Interconnects

2011 ◽  
Author(s):  
Subramanya Sadasiva ◽  
Ganesh Subbarayan ◽  
Lei Jiang ◽  
Daniel Pantuso
Keyword(s):  
Flip Chip ◽  
Field Model ◽  
Solder Joints ◽  
Equations Of Motion ◽  
Phase Field Model ◽  
Solder Interconnects ◽  
Energy Stress ◽  
Current Densities ◽  
Void Propagation ◽  
Free Solder

Increasing miniaturization has led a significant increase in the current densities seen in flip-chip solder joints. This has made the study of failure in solder joints by void propagation due to electromigration and stress migration more important. In this study, we develop a phase field model for the motion of voids through a flip chip solder interconnect. We derive equations of motion for the void accounting for energetic contributions from the active factors of surface energy, stress and electric potential, taking into account both surface diffusion and transfer of the material through the bulk of the material. We describe the implementation of this model using finite elements, coupled with a commercial finite element solver to solve for the fields driving the void motion.

Interfacial Morphology and Shear Deformation of Flip Chip Solder Joints

2000 ◽  
Vol 15 (8) ◽  
pp. 1679-1687 ◽  
Author(s):  
J. W. Jang ◽  
C. Y. Liu ◽  
P. G. Kim ◽  
K. N. Tu ◽  
A. K. Mal ◽  
...  
Keyword(s):  
Shear Deformation ◽  
Dielectric Layer ◽  
Flip Chip ◽  
Solder Joints ◽  
Organic Substrate ◽  
Failure Behavior ◽  
Interfacial Morphology ◽  
Solder Interconnects ◽  
Solder Balls ◽  
Electroless Ni

We examined the interfacial morphology and shear deformation of flip chip solder joints on an organic substrate (chip-on-board). The large differences in the coefficients of thermal expansion between the board and the chip resulted in bending of the 1-cm2 chip with a curvature of 57 ± 12 cm. The corner bump pads on the chip registered a relative misalignment of 10 μm with respect to those on the board, resulting in shear deformation of the solder joints. The mechanical properties of these solder joints were tested on samples made by sandwiching two Si chips with electroless Ni(P) as the under-bump metallization and 25 solder interconnects. Joints were sheared to failure. Fracture was found to occur along the solder/Ni3Sn4 interface. In addition, cracking and peeling damages of the SiO2 dielectric layer were observed in the layer around the solder balls, indicating that damage to the dielectric layer may have occurred prior to the fracture of the solder joints due to a large normal stress. The failure behavior of the solder joints is characterized by an approximate stress analysis.

Characterization of Die Stresses in CBGA Packages due to Component Assembly and Heat Sink Clamping

2011 ◽  
Author(s):  
Jordan C. Roberts ◽  
Mohammad Motalab ◽  
Safina Hussain ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
...  
Keyword(s):  
Heat Sink ◽  
Flip Chip ◽  
Solder Joints ◽  
Ceramic Substrate ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Interconnects ◽  
Die Stress ◽  
Free Solder ◽  
Test Chips

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level CBGA solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, we have used test chips containing piezoresistive sensors to measure the buildup of mechanical stresses in a microprocessor die after various steps of the CBGA assembly process, as well as due to heat sink clamping. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses have been found to increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, lid attachment, CBGA assembly to PCB, and heat sink clamping). Levels exceeding 500 MPa have been observed for extremely high heat sink clamping forces. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the individual test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. A metallic lid and second level solder balls were attached to complete the flip chip ceramic BGA components. After every packaging step (flip chip solder ball reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. Finally, CBGAs with the stress sensing chips were soldered to organic PCB test boards. A simulated heat sink loading was then applied, and the stresses were measured as a function of the clamping force. The heat sink clamping pressure distribution was monitored using in-situ resistive sensors in the TIM2 position between the lid and heat sink. The measured stress changes due to heat sink clamping where correlated with finite element simulations. With suitable detail in the models, excellent correlation has been obtained.

Numerical Simulations of Electromigration and Stressmigration Driven Void Evolution in Solder Interconnects

2012 ◽  
Vol 134 (2) ◽  
Author(s):  
Subramanya Sadasiva ◽  
Ganesh Subbarayan ◽  
Lei Jiang ◽  
Daniel Pantuso
Keyword(s):  
Finite Element ◽  
Flip Chip ◽  
Solder Joints ◽  
High Current Density ◽  
Equations Of Motion ◽  
Void Formation ◽  
Phase Field Model ◽  
Bulk Diffusion ◽  
Stress Fields ◽  
Void Evolution

Understanding the effect of high current density on void formation and growth and relating the size of the void to the resulting electrical/mechanical failure is a critical need at the present time to ensure reliable functioning of flip-chip packages. In general, toward this end, the modeling and simulation of geometrical evolution of current induced voids have been relatively few. Simulations considering the coupled effects of mass transport through mechanisms of surface and bulk diffusion under the influence of electrical, thermal, and stress fields in solder joints leading to eventual electromigration failure do not appear to be common. In this study, we develop a phase field model for the evolution of voids under electrical, thermal, and stress fields in a flip-chip solder interconnect. We derive the equations of motion for the void accounting for energetic contributions from the active factors of surface energy, stress, and electric potential, considering both surface diffusion and transfer of the material through the bulk of the material. We describe the implementation of this model using a finite element code written in the PYTHON language, coupled with a commercial finite element solver from which we obtain the electrical, thermal, and stress fields driving the void motion. We demonstrate the implemented methodology through simulations of void evolution in flip-chip solder joints under the effects of mechanical/electrical fields and surface/bulk diffusion.

scholarly journals Electromigration Mechanism of Failure in Flip-Chip Solder Joints Based on Discrete Void Formation

2017 ◽  
Vol 7 (1) ◽  
Author(s):  
Yuan-Wei Chang ◽  
Yin Cheng ◽  
Lukas Helfen ◽  
Feng Xu ◽  
Tian Tian ◽  
...  
Keyword(s):  
Flip Chip ◽  
Solder Joints ◽  
Void Formation ◽  
Mechanism Of Failure
Sign in / Sign up

Export Citation Format

Share Document