Fatigue Analysis of a Ceramic Pin Grid Array Soldered to an Orthotropic Epoxy Substrate

1991 ◽  
Vol 113 (2) ◽  
pp. 138-148 ◽  
Author(s):  
J. Lau ◽  
R. Subrahmanyan ◽  
D. Rice ◽  
S. Erasmus ◽  
C. Li
Keyword(s):  
Thermal Expansion ◽  
Solder Joint ◽  
Normal Stress ◽  
Printed Circuit Board ◽  
Thermal Stresses ◽  
Circuit Board ◽  
Thermal Expansion Mismatch ◽  
Stress Strain ◽  
Plated Through Hole ◽  
Through Hole

Thermal stresses and strains in the solder joints and plated-through-hole (PTH) copper pads/barrels of a pin-grid array (PGA) assembly under thermal cycling conditions have been determined in the present study. There are two major systems of thermal stresses/strains acting at the solder joint and copper. One is the transverse shear and vertical normal stress/strain due to the local thermal expansion mismatch between the pin, solder, copper, and FR-4. The other is the horizontal normal stress/strain due to the global thermal expansion mismatch between the ceramic PGA and the FR-4 printed circuit board (PCB). The effects of the local thermal expansion mismatch on the reliability of solder joint and PTH copper have been determined using a 3-D orthotropic-elastoplastic finite element method. The effects of the global thermal expansion mismatch on the reliability of solder joint and PTH copper have been determined by fatigue experiments. Fatigue life of the solder joint and PTH copper was then estimated based on the calculated strains and the fatigue data on solders and coppers.

Thermal Model of Printed Circuit Board Plated-Through Hole under One-Sided Heating Conditions

2021 ◽  
Vol 26 (5) ◽  
pp. 426-431
Author(s):  
V.A. Sergeev ◽  
◽  
A.M. Khodakov ◽  
M.Yu. Salnikov ◽  
◽  
...  
Keyword(s):  
Quality Control ◽  
Thermal Resistance ◽  
Thermal Model ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Thermal Models ◽  
Printed Circuit ◽  
Plated Through Hole ◽  
Through Hole

Thermal methods of quality control of the plated-through hole (PTH) of printed circuit board (PCB) are based on thermal models. However, known thermal models of PTH take no account of heat transfer to PCB material thus not allowing for PTH heat characteristic tying up with adhesion quality. In this work, an axisymmetric thermal model of a single-layer PCB PTH under one-sided heating conditions is considered. It was shown that the ratio of the temperature increments of the upper (heated) and lower end of the PTH in the considered range of heating power does not depend on the power level. A linear thermal equivalent scheme of the PTH has been proposed, which includes the longitudinal thermal resistance of the PTH metallization, de-termined by the parameters and quality of the metallization layer, the thermal resistance, which determines the convection heat exchange between the ends of the PTH with the adjacent PCB surface and the environment, and the thermal resistance of the area of the PCB material adjacent to the PTH, depending on the quality of the metallization adhesion and the PCB dielectric. Thermal equivalent circuit parameters determined by the ratio of the temperature increment of the upper and lower ends of the PTH and their difference can serve as the basis for the development of a nondestructive inspection procedure for PTH quality control by way of its unilateral heating, for example, by a laser beam.

TEM Analysis of Printed Circuit Board Copper Foil

1980 ◽  
Vol 38 ◽  
pp. 408-409
Author(s):  
Ron Anderson ◽  
Roger Wild
Keyword(s):  
Copper Foil ◽  
Printed Circuit Board ◽  
Stress Test ◽  
Thermal Exposure ◽  
Circuit Board ◽  
Tem Analysis ◽  
Plated Through Hole ◽  
Columnar Grain ◽  
Test Requirements ◽  
Through Hole

Approximately two years ago, electro-deposited (ED) copper foil cracking was noticed when testing relatively high density, highly stressed multilayer boards (MLBs) to the rigid 55()°F thermal stress test requirements of MIL-P-55640 and eventually MIL.-P-551 IOC. This ED copper foil cracking is basically caused by severe plated through hole (PTH) bending forces caused by the large difference in thermal expansions between the copper PTH barrel and the epoxy glass resin within the multilayer board at high soldering lemperatures. The severity of the copper foil cracking would be dependent on the basic thermal mismatch of MLB materials; the severity of thermal exposure; the specific design impacts; and the mechanical properties of the copper foil. Copper foil cracks develop circumferentially around the PTH barrel within the relatively weak columnar grain boundaries of the ED copper foil. Generally, cracks occur quite close (within 2 mils) of the PTH barrel wall with cracking or fracturing being more dominant on the first and last internal foil layers within the board.

Stereoimaging Determination of Strains in Surface Mounted Components and Plated Through Holes Resulting from Thermal Cycung

1991 ◽  
Vol 226 ◽  
Author(s):  
David L. Davidson
Keyword(s):  
Printed Circuit Board ◽  
High Spatial Resolution ◽  
Circuit Board ◽  
Depth Of Field ◽  
Scanning Microscope ◽  
Printed Circuit ◽  
Plated Through Hole ◽  
Microelectronic Components ◽  
Through Hole

AbstractThe experimental mechanics of microelectronics components requires high spatial resolution measurements that are best obtained by using the scanning microscope because of the high spacial resolution and depth of field obtained using this instrument. This paper describes how measurements made from photographs taken in the scanning electron microscope have been used successfully to determine the strains which develop due to differences in coefficient of thermal between various parts of microelectronic components. Results are presented for thermal strains in the solder joints of a surface mounted component and in a printed circuit board plated through hole.

A Study of Solder Paste Rheology for The Alternative Assembly and Reflow Technology (AART) Process

1998 ◽  
Vol 515 ◽  
Author(s):  
S.T. Murthy ◽  
D. Manessis ◽  
K. Srihari ◽  
G.R. Westby
Keyword(s):  
Yield Stress ◽  
Printed Circuit Board ◽  
Shear Thinning ◽  
Circuit Board ◽  
Print Quality ◽  
Solder Paste ◽  
Assembly Process ◽  
Pcb Assembly ◽  
Plated Through Hole ◽  
Through Hole

ABSTRACTSolder paste performance related properties such as stencil print quality, viscosity, thixotropy, and slump resistance are of great importance in the pre-reflow stages of the electronics assembly process. This paper focuses on the study of the rheological behavior of solder paste and its correlation to process performance during the various steps of the Alternative Assembly and Reflow Technology (AART) process. This technology aims to integrate the Printed Circuit board (PCB) assembly process for both through hole and surface mount components. Four solder pastes were considered in this study and their rheological characteristics were identified through flow and oscillation tests. The oscillation tests provided the linear viscoelastic characteristics of solder paste whereas the flow tests revealed information on the yield stress as well as the degree of shear-thinning and thixotropy of the solder paste. Pastes with high elastic properties and yield stress exhibited good hot slump resistance. Furthermore, extensive shear thinning of the paste facilitated the filling of the Plated-Through-Hole (PTH) sites. Recommendations are provided for tailoring the properties of a solder paste to meet the needs of the AART process.

Analysis of Thermal Stresses in a Layered Circuit Board

2001 ◽  
Author(s):  
James C. Gerdeen
Keyword(s):  
Thermal Expansion ◽  
Printed Circuit Board ◽  
Thermal Stresses ◽  
Circuit Board ◽  
Shear Stresses ◽  
Optimum Ratio ◽  
Design Guideline ◽  
One Dimensional ◽  
Printed Circuit ◽  
Conduction Heat Flow

Abstract When choosing materials for a printed circuit board (PCB), it appears that a common misconception is that the coefficients of thermal expansion should be matched as closely as possible to minimize the stresses. In this paper it is shown that this is not necessarily true. A one-dimensional thermal stress analysis is considered for a printed circuit board (PCB) with N layers. Bending is neglected and average axial normal stresses and shear stresses are accounted for. It is shown that the solution for the shear stresses between layers can be written in the form of a difference equation (recurrence relation). For the first example, a two-layer board is considered. The solution leads to a design guideline. If there is a shear stress design limit then based on this a plot can be made to choose the optimum ratio of CTEs for the layers depending upon whether the conduction heat flow q is zero or not and depending upon magnitude of temperature change.. If q = 0, then matching the coefficients of expansion α1 and α2 reduces the stress to zero. However if q is not zero at some times, then a choice of the CTE ratio α1/α2 should be made to keep the stress between the design limits. For three or more layers with different properties a design optimization scheme can be used to choose values of the coefficients of thermal expansion.

Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint

2004 ◽  
Author(s):  
Norman J. Armendariz ◽  
Prawin Paulraj
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Gold Surface ◽  
Circuit Board ◽  
Lead Free ◽  
Processing Temperature ◽  
The European Union ◽  
Printed Circuit ◽  
Higher Temperature ◽  
Tin Silver Copper

Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

Sign in / Sign up

Export Citation Format

Share Document