Effect of Shield-Can on Dynamic Response of Board-Level Assembly

2012 ◽  
Vol 134 (3) ◽  
Author(s):  
Da Yu ◽  
Jae Kwak ◽  
Seungbae Park ◽  
Soonwan Chung ◽  
Ji-Young Yoon

In order to protect the electronic components of electronic devices on a printed circuit board (PCB) against electromagnetic radiation, a conductive shield-can or box is normally attached to the PCB covering the electronic components. In particular, handheld electronic devices are prone to be subjected to drop impact. This means that the products would experience a significant amount of out-of-plane deformation along the PCB, which may cause stresses eventually resulting in solder joint failures. The attached shield-can could provide additional mechanical strength and minimize the out-of-plane deformation, especially where the electronic package is located. In this study, both the dynamic responses of the PCB and the characteristic life of solder joints with different shield-can designs were investigated, which are seldom explored by other researchers. In the board-level drop tests, a noncontact full-field optical measurement technique, digital image correlation (DIC) with images taken by stereo-high-speed cameras, was used to obtain full-field displacement data showing the dynamic responses of the PCB during the drop impact. PCBs with a fine ball grid array (FBGA) package were prepared with various types of shield-can attached. From the experimental results the effects of different shield-can types, varying in shape and size on the dynamic responses of the PCB, were analyzed. In addition, the number of drops to failure for each shield-can was also recorded by an event detector. Using ANSYS/LS-DYNA, an accurately validated finite element model has been developed. Then the stress analysis could be performed in order to study the failure mechanism by finding the maximum tensile stress of the solder joints during the drop impact and correlate the stress results with the characteristic life of solder joint.

Author(s):  
Da Yu ◽  
Jae B. Kwak ◽  
Seungbae Park ◽  
Soonwan Chung ◽  
Ji-Young Yoon

When a handheld device is subjected to a drop impact, the out-of-plane deformation of printed circuit board (PCB) is a major concern to manufacturers as it is directly proportional to the stress which causes failure for the solder joints. The shield-can attached to the PCB can provide additional mechanical strength and minimize the out-of-plane deformation. In this work, board level drop test is conducted with instrumentation following the Joint Electron Device Engineering Council (JEDEC) test standards. A non-contact full field optical measurement technique, Digital Image Correlation (DIC), is applied to monitor and document the dynamic responses of PCB during the drop test. Different shield-can type varying in shape and size are attached to the PCB through frame or clip type connection. The effects of these two connecting methods, as well as the shape and size of shield-can, on the dynamic responses of PCB are analyzed experimentally. Along with board level drop experiments, a detailed 3D FEA model has been developed to verify and analyze the dynamic responses of PCB using ANSYS/LS-DYNATM. Several simulations have been performed to verify experimental results. Different contact techniques, such as Nodes merge and Tied Nodes to Surface (TDNS) contact have been applied as boundary conditions to connect shield-can with PCB and a proper representation of connection is found in the simulation.


2012 ◽  
Vol 134 (4) ◽  
Author(s):  
D. N. Borza ◽  
I. T. Nistea

Reliability of electronic assemblies at board level and solder joint integrity depend upon the stress applied to the assembly. The stress is often of thermomechanical or of vibrational nature. In both cases, the behavior of the assembly is strongly influenced by the mechanical boundary conditions created by the printed circuit board (PCB) to casing fasteners. In many previously published papers, the conditions imposed to the fasteners are mostly aiming at an increase of the fundamental frequency and a decrease of static or dynamic displacement values characterizing the deformation. These conditions aim at reducing the fatigue in different parts of these assemblies. In the photomechanics laboratory of INSA Rouen, the origins of solder joint failure have been investigated by means of full-field measurements of the flexure deformation induced by vibrations or by forced thermal convection. The measurements were done both at a global level for the whole printed circuit board assembly (PCBA) and at a local level at the solder joints where failure was reported. The experimental technique used was phase-stepped laser speckle interferometry. This technique has a submicrometer sensitivity with respect to out-of-plane deformations induced by bending and its use is completely nonintrusive. Some of the results were comforted by comparison with a numerical finite elements model. The experimental results are presented either as time-average holographic fringe patterns, as in the case of vibrations, or as wrapped phase patterns, as in the case of deformation under thermomechanical stress. Both types of fringe patterns may be processed so as to obtain the explicit out-of-plane static deformation (or vibration amplitude) maps. Experimental results show that the direct cause of solder joint failure may be a high local PCB curvature produced by a supplementary fastening screw intended to reduce displacements and increase fundamental frequency. The curvature is directly responsible for tensile stress appearing in the leads of a large quad flat pack (QFP) component and for shear in the corresponding solder joints. The general principle of increasing the fundamental frequency and decreasing the static or dynamic displacement values has to be checked against the consequences on the PCB curvature near large electronic devices having high stiffness.


2011 ◽  
Vol 423 ◽  
pp. 26-30
Author(s):  
S. Assif ◽  
M. Agouzoul ◽  
A. El Hami ◽  
O. Bendaou ◽  
Y. Gbati

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.


2011 ◽  
Vol 133 (3) ◽  
Author(s):  
Tong An ◽  
Fei Qin

The significant difference between failure modes of lead-containing and lead-free solder joints under drop impact loading remains to be not well understood. In this paper, we propose a feasible finite element approach to model the cracking behavior of solder joints under drop impact loading. In the approach, the intermetallic compound layer/solder bulk interface is modeled by the cohesive zone model, and the crack driving force in the intermetallic compound layer is evaluated by computing the energy release rate. The numerical simulation of a board level package under drop impact loading shows that, for the lead-containing Sn37Pb solder joint, the damage in the vicinity of the intermetallic compound layer initiates earlier and is much greater than that in the lead-free Sn3.5Ag solder joint. This damage relieves the stress in the intermetallic compound layer and reduces the crack driving force in it and consequently alleviates the risk of the intermetallic compound layer fracturing.


Author(s):  
Shi-Wei Ricky Lee ◽  
Yin-Lai Tracy Li ◽  
Hoi-Wai Ben Lui

The present study is intended to investigate the board level solder joint reliability of PBGA assemblies under mechanical drop test. During the course of this study, a five-leg experiment was designed to investigate various combinations of solder materials and peak reflow temperatures. Two major failure modes, namely, solder cracking and copper trace breakage, were identified. In addition, the critical location of solder joints was characterized. It was found that Sn-Pb eutectic solder joints performed better than Pb-free solder joints under mechanical impact loading.


2012 ◽  
Vol 50 (4) ◽  
pp. 529-533 ◽  
Author(s):  
Lei Huang ◽  
Chi Seng Ng ◽  
Anand Krishna Asundi

2010 ◽  
Vol 34-35 ◽  
pp. 451-455
Author(s):  
Fang Liu ◽  
Guang Meng

Finite element (FE) method is an efficient and power tool, and is adopted to analyze dynamic response of printed circuit board (PCB) assembly. First, FE model of PCB assembly was established. Second, the dynamic behaviors of ball gird array (BGA) lead-free solder joint were obtained when the PCB assembly was subjected to a half-sine acceleration pulse. Results show that the maximum tensile stresses occur at solder joints located at the four outermost corners of BGA and solder joints at outermost corners are the most vulnerable to crack. In addition, it can be found during FE analysis that the solder joint reliability can be enhanced as the PCB damping increases and input acceleration level reduces.


2011 ◽  
Vol 64 (2) ◽  
Author(s):  
Y. H. Yau ◽  
Shijie Norman Hua

This article is dedicated to the review of publications on drop impact analysis performed on consumer electronic devices such as cellular phones and two-way radios in the past decade. Prior to the highlights of this review, the scope and motivation behind this work will be briefly explained. A comprehensive survey on published literatures devoted to the methodologies established to analyze the reliability of electronic products exposed to the event of drop impact is presented. The scope of the review is extended beyond product level analysis to also include drop impact study at board level. This type of review is novel and has not been published in the past. The focus will be on the different analytical and numerical modeling approaches and the current status of finite element method in predicting the drop impact performance of electronic devices. Of equal interest is the methodology adopted in past work to establish a correlation between numerical and experimental results. This article serves as a reference to all intended future work which could be an extension from the current known art of drop impact analysis on electronic devices. The time frame of this review is up to year 2010.


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