Examination of the Slip Boundary Condition by µ-PIV and Lattice Boltzmann Simulations

This work examines the slip boundary condition by Lattice Boltzmann simulations, addresses the validity of the Navier’s hypothesis that the slip velocity is proportional to the shear rate and compares the Lattice Boltzmann simulations to the experimental results of Tretheway and Meinhart (Phys. of Fluids, 14, L9–L12). The numerical simulation models the boundary condition as the probability, P, of a particle to bounce-back relative to the probability of specular reflection, 1−P. For channel flow, the numerically calculated velocity profiles are consistent with the experimental profiles for both the no-slip and slip cases. No-slip is obtained for a probability of 100% bounce-back, while a probability of 0.03 is required to generate a slip length and slip velocity consistent with the experimental results of Tretheway and Meinhart for a hydrophobic surface. The simulations indicate that for microchannel flow the slip length is nearly constant along the channel walls, while the slip velocity varies with wall position as a results of variations in shear rate. Thus, the resulting velocity profile in a channel flow is more complex than a simple combination of the no-slip solution and slip velocity as is the case for flow between two infinite parallel plates.

Elastic Modulus of Pb/Sn Solder Joints in Microelectronics

Young’s modulus (E) values published in literature for the eutectic Pb37/Sn63 and near eutectic Pb40/Sn60 solder alloy vary significantly. One reason for this discrepancy is different testing methods for highly rate sensitive heterogeneous materials, like Pb/Sn alloys, yield different results. In this paper, we study different procedures used to obtain the elastic modulus; analytically, by single crystal elasticity and experimentally by ultrasonic testing and Nano indentation. We compare these procedures and propose a procedure for elastic modulus determination. The deformation kinetics of the Pb/Sn solder alloys is discussed at the grain size level.

A Statistical Approach to Improve Wafer Fabrication Yield

In spite of the recent advancements in wafer fabrication techniques, devices are still being individually checked and modified. This is due to the fact that the general manufacturing processes involved in wafer production have their inherent inconsistencies. As a consequence, individual devices show differences in characteristics that would render a big group of them operating out of the range of the pre-set spec limits. Therefore they would require types of modifications specific to the individual device. Knowing that the resources spent on checking and eliminating out-of-spec devices before they reach the customer are very significant, the manufacturing operation becomes hardly profitable. These wafers normally carry devices in the range of a thousand or so, making a statistical approach very attractive. In this paper, an actual industrial problem in wafer fabrication to the desired specifications is presented. The problem shows in passive filters built using Surface Acoustic Wave (SAW) theory. A solution considering a statistical process control approach to the population of devices on the wafer is proposed. The results of applying this solution are realized in significant product yield increase, huge cost cutting, and automation promotion and application.

Ultrasonic Rapid Manufacturing: Implementation and Thermo-Mechanical Analysis

This paper addresses a novel non-thermal Ultrasonic Rapid Manufacturing (URM), for layered parts based on Ultrasonic Metal Welding (USW). Its laboratory implementation, automation and integration are described first. The thermo-mechanical process aspects (i.e. heat generation and resulting temperature effects) during each cycle of ultrasonic welding are then studied. The technical advantages of ultrasonic welding process, including fabrication of dense, full-strength functional solid metal parts, multi-material composites, and active parts with embedded intelligent components and electronic, mechatronic, optic and fluidic structures, are examined.

Optimization of Multiple Head SMT Placement Machine: Model and Approaches

In order to maximize the throughput rate of single multiple head surface mounted technology placement machine, the time taken for pick-and-place of components for each printed circuit board has to be minimized. This gives rise to two related essential problems, namely feeder assignment problem and pick-and-place sequence determination problem. In this paper, we introduce a model that simplifies problems. We regard all components during a pick-and-place cycle as a unit and give it a matching weight. In this way, we change multiple head machine problems into single head machine problems. The optimisation problem becomes two sub-problems: minimum weight matching problem and travelling salesman problem of these units. We presented algorithms to obtain near optimal solution and implement them as a computer program. We performed experiment on a real four head placement machine. The experimental results are presented to analyse their performance.

Low Temperature Anodic Bonding for MEMS Applications

In this paper, anodic bonding between silicon wafer and glass wafer (Pyrex 7740) has been successfully achieved at low temperature. The bonding strength is measured using a tensile testing machine. The interfaces are examined and analyzed by scanning acoustic microscopy (SAM), scanning electron microscopy (SEM) and secondary ion mass spectrometry (SIMS). Prior to bonding, the wafers are cleaned in RCA solutions, and the surfaces become hydrophilic. The effects of the bonding parameters, such as bonding temperature, voltage, bonding time and vacuum condition, on bonding quality are investigated using Taguchi method, and the feasibility of bonding silicon and glass wafers at low temperature is explored. The bonding temperature used ranges from 200 °C to 300 °C. The sensitivity of the bonding parameters is analyzed and it is found that the bonding temperature is the dominant factor for the bonding process. Therefore, the effects of bonding temperature are investigated in detail. High temperatures cause high ion mobility and bonding current density, resulting in the short transition period to the equilibrium state. Almost bubble-free interfaces have been obtained. The bonded area increases with increasing the bonding temperature. The unbonded area is less than 1.5% within the whole wafer for bonding temperature between 200 °C to 300 °C. The bonding strength is higher than 10 MPa, and increases with the bonding temperature. Fracture mainly occurs inside the glass wafer other than in the interface when the bonding temperature is higher than 225 °C. SIMS results show that the chemical bonds of Si-O form in the interface. Higher bonding temperature results in more oxygen migration to the interface and more Si-O bonds. The bonding mechanisms consist of hydrogen bonding and Si-O chemical reaction.

Process-Induced Thermal Effect on Packaging Yield of RF MEMS Switches

RF MEMS switches offer significant performance advantages in high frequency RF applications. The switches are actuated by electrostatic force when voltage was applied to the electrodes. Such devices provide high isolation when open and low contact resistance when closed. However, during the packaging process, there are various possible failure modes that may affect the switch yield and performance. The RF MEMS switches were first placed in a package and went through lid seal at 320°C. The assembled packages were then attached to a printed circuit board at 220°C. During the process, some switches failed due to electrical shorting. More interestingly, more failures were observed at the lower temperature of 220°C rather than 320°C. The failure mode was associated with the shorting bar and the cantilever design. Finite element simulations and simplified analytical solutions were used to understand the mechanics driving the behaviors. Simulation results have shown excellent agreement with experimental observations and measurements. Various solutions in package configurations were explored to overcome the hurdles in MEMS packaging and achieve better yield and performance.

Evaluation of a Conductive Adhesive Based Approach to Lead Free Flip Chip Assembly

Electrically conductive adhesives are emerging as a lead free, flux less, low temperature alternative to soldering in a variety of electronics and optoelectronics applications. Some of the potential benefits are obvious, but so far the adhesives have some limitations as well. The present work offers a critical evaluation of one approach to flip chip assembly, which lends itself particularly well to use with a high speed placement machine. Wafers were bumped by stencil printing of a thermoset conductive adhesive, which was then fully cured. In assembly, the conductive adhesive paste was stencil printed onto the pads of a printed circuit board and cured after die placement. The printing process was optimized to ensure robust assembly and the resulting reliability assessed.

Reliability Evaluation of CSP Using New Flip-Chip Bonding Technology: Both-Sided CSP and Single-Sided CSP

Chip-size packaging (CSP) attracts largely attentions due to its lighter, thinner and smaller size. In this study, the deformations and the stresses in the CSP fabricated by non-conductive film stud-bump direct interconnection (NSD) were analyzed. The reliability evaluation of single-sided CSP and both-sided CSP were investigated for heat cycles. The material parameters, i.e. stresses, strains and deformations, for achieving a high reliability of CSP were investigated using a finite element method and experiment. The dependency of the life in single-sided CSP and both-sided CSP on the thicknesses of IC and substrate could be expressed using a normal stress in the thickness direction and shear stress in the vertical cross section, respectively.

Process-Induced Stress Effect on Reliability of ChipSeal® Passivation Technology

It is important to take into consideration the process-induced residual stress into reliability prediction modeling. Lack of process-induced stress may lead to error in reliability prediction. Therefore, careful investigation of the stress development is critical. In this paper, the stress development induced by ChipSeal® passivation process technology has been analyzed. The ChipSeal® passivation technology has been developed to enhance the reliability of commercially-off-the-shelf plastic encaptulated microelectronics component by sealing integrated circuit at the wafer level. The analysis takes every process step into account to investigate the temperature effect on the final residual stress. The section of the fabricated structure has been modeled in two different configurations. The stress developments have been simulated by numerical method, and the results have been analyzed to identify the critical location. Three different lengths of metal layer have been considered to investigate the effect of metal layer length structure. Finally, a response surface method is employed to determine the thickness effect of individual layers and to develop design guidelines to enhance ChipSeal® reliability.