Power and Thermal Constraints-Driven Modeling and Optimization for Through Silicon Via-Based Power Distribution Network

2018 ◽  
Vol 140 (4) ◽  
Author(s):  
Weijun Zhu ◽  
Gang Dong ◽  
Yintang Yang
Keyword(s):  
Power Distribution ◽  
Rational Design ◽  
Voltage Drop ◽  
Three Dimensional ◽  
Power Delivery ◽  
Power Distribution Network ◽  
Through Silicon Via ◽  
Power Delivery Network ◽  
Thermal Constraints ◽  
Global Power

The design of three-dimensional (3D) power delivery network (PDN) is constrained by both power and thermal integrity. Through-silicon via (TSV) as an important part of transmission power and heat in stack, the rational design of TSV layout is particularly important. Using minimal TSV area to achieve the required 3D PDN is significant to reduce manufacturing costs and increase integration. In this paper, we propose electrical and thermal models of 3D PDN, respectively, and we use them to solve the 3D voltage drop and temperature distribution problems. The accuracy and efficiency of our proposed methods are demonstrated by simulation measurement. Combining these two methods, a layer-based optimization solution is developed and allows us to adjust the TSV density for different layers while satisfying the global power and thermal constraints. This optimization is scalable and has the same guiding value for multichip stacks with different functions and constraints. A setup of four-chip stack is used to demonstrate the feasibility of this optimization and a large TSV area saving is achieved by this method.

Development of Backside Buried Metal Layer Technology for 3D-ICs

2019 ◽  
Vol 2019 (1) ◽  
pp. 000268-000273
Author(s):  
Naoya Watanabe ◽  
Yuuki Araga ◽  
Haruo Shimamoto ◽  
Katsuya Kikuchi ◽  
Makoto Nagata
Keyword(s):  
Integrated Circuits ◽  
Metal Layer ◽  
Three Dimensional ◽  
Chip Thickness ◽  
Power Delivery ◽  
Silicon Structure ◽  
Metal Insulator ◽  
3D Ics ◽  
Power Delivery Network ◽  
Global Power

Abstract In this study, we developed backside buried metal (BBM) layer technology for three-dimensional integrated circuits (3D-ICs). In this technology, a BBM layer for global power routing is introduced in the large vacant area on the backside of each chip and is parallelly connected with the frontside routing of the chip. The resistances of the power supply (VDD) and ground (VSS) lines consequently decrease. In addition, the BBM structure acts as a decoupling capacitor because it is buried in the Si substrate and has metal–insulator–silicon structure. Therefore, the impedance of power delivery network can be reduced by introducing the BBM layer. The fabrication process of the BBM layer for 3D-ICs was simple and compatible with the via-last through-silicon via (TSV) process. With this process, it was possible to fabricate the BBM layer consisting of electroplated Cu (thickness: approximately 10 μm) buried in the backside of the CMOS chip (thickness: 43 μm), which was connected with the frontside routing of the chip using 9 μm-diameter TSVs.

scholarly journals The maximum voltage drop in an on-chip power distribution network: analysis of square, triangular and hexagonal power pad arrangements

2014 ◽  
Vol 25 (5) ◽  
pp. 531-551
Author(s):  
TOM CARROLL ◽  
JOAQUIM ORTEGA-CERDÀ
Keyword(s):  
Power Distribution ◽  
Complex Analysis ◽  
Voltage Drop ◽  
Elliptic Functions ◽  
Distribution Networks ◽  
Power Distribution Networks ◽  
Power Distribution Network ◽  
On Chip ◽  
Geometric Arrangements ◽  
Maximum Voltage

A mathematical model of the voltage drop which arises in on-chip power distribution networks is used to compare the maximum voltage drop in the case of different geometric arrangements of the pads supplying power to the chip. These include the square or Manhattan power pad arrangement, which currently predominates, as well as equilateral triangular and hexagonal arrangements. In agreement with the findings in the literature and with physical and SPICE models, the equilateral triangular power pad arrangement is found to minimize the maximum voltage drop. This headline finding is a consequence of relatively simple formulas for the voltage drop, with explicit error bounds, which are established using complex analysis techniques, and elliptic functions in particular.

scholarly journals On an asymptotic formula for the maximum voltage drop in a on-chip power distribution network

2011 ◽  
Vol 23 (2) ◽  
pp. 245-265 ◽  
Author(s):  
MARIA AGUARELES ◽  
JAUME HARO ◽  
JOSEP RIUS ◽  
J. SOLÀ-MORALES
Keyword(s):  
Integrated Circuits ◽  
Asymptotic Formula ◽  
Power Distribution ◽  
Voltage Drop ◽  
Special Functions ◽  
Distribution Networks ◽  
Power Distribution Networks ◽  
Power Distribution Network ◽  
On Chip ◽  
Solutions Of Equations

We present a new asymptotic formula for the maximum static voltage in a simplified model for on-chip power distribution networks of array bonded integrated circuits. In this model the voltage is the solution of the Poisson's equation in an infinite planar domain whose boundary is an array of circular pads of radius ϵ, and we deal with the singular limit ϵ → 0 case. In comparison with approximations that appear in the electronics engineering literature, our formula is more complete, since we have obtained terms up to order ϵ15. A procedure will be presented to compute all the successive terms, which can be interpreted by using multipole solutions of equations involving spatial derivatives of δ-functions. To deduce the formula, we use the method of matched asymptotic expansions. Our results are completely analytical and we make an extensive use of special functions and the Gauss constant G.

scholarly journals Power Distribution Network Based on Digital 3D Twin Panoramic Modeling

2020 ◽  
Vol 204 ◽  
pp. 02005
Author(s):  
Zhan Chao ◽  
Luo Yizhao ◽  
Li Ronggui ◽  
Gao Jun ◽  
Zhang Mi
Keyword(s):  
Power Distribution ◽  
Power Grid ◽  
Distribution Network ◽  
Three Dimensional ◽  
Current Method ◽  
Virtual Space ◽  
Power Distribution Network ◽  
Digital Twins ◽  
Average Current ◽  
Line Loss

Digital twins refer to virtual digital expressions constructed in virtual space that can characterize characteristics, the formation process and behavior of natural entities, and it has the characteristics of multi-physics, multi-scale and probability. This article mainly introduces the application research of digital 3D twin panorama modeling in power distribution network. This paper proposes the average current method to calculate the line loss of the power distribution network, so that the accuracy is guaranteed. In addition, the digital three-dimensional panoramic modeling method is used to optimize the grid system, and the data structure is used to calculate the power distribution network. Analyze the topological structure of the power grid, and then obtain the calculation method of the distribution network line loss. The experimental results in this paper show that the rendering efficiency of power grid results has increased by 17% based on the digital 3D twin panorama modeling, and the method and algorithm for matching video and panorama image are proposed, which solves the problem of video rotation angle on the panorama connection, so that The smoothness of panoramic roaming is improved by 23%.

Analysis on Signal and Power Integrity of 2.3D Structure Organic Package

2019 ◽  
Vol 2019 (1) ◽  
pp. 000381-000386 ◽  
Author(s):  
Kosuke Tsukamoto ◽  
Atsunori Kajiki ◽  
Yuji Kunimoto ◽  
Masayuki Mizuno ◽  
Manabu Nakamura ◽  
...  
Keyword(s):  
Power Distribution ◽  
Signal Integrity ◽  
High Density ◽  
Point Of View ◽  
Power Delivery ◽  
Power Integrity ◽  
Power Distribution Network ◽  
Organic Packages ◽  
High Bandwidth ◽  
Vertical Interconnection

Abstract Heterogeneous packaging is one of the advanced technologies. Especially for high-end applications such as data center server, HPC and Artificial-Intelligence (AI), High-Bandwidth Memory (HBM) integration is a key and strongly required. As we know, the 2.5D silicon interposer packaging is an expanded solution for HBM interconnections. However, we developed 2.1D high density organic package called i-THOP® (integrated-Thin film High density Organic Package) to take advantages of an organic solution. Furthermore, we are now focusing on 2.3D i-THOP® to have more benefits in the manufacturing. The 2.3D structure consists of two substrates. One is a thin i-THOP® interposer, the other one is a conventional build-up (BU) substrate. These two substrates are combined as the interposer placed onto the build-up substrate. In this paper, the electrical properties of 2.3D i-THOP® are studied to confirm the possibility of the 2.3D structure organic packages from the perspective of signal and power integrity. Firstly, the signal integrity between two devices is simulated, comparing the differences between i-THOP® and the 2.5D silicon interposer. Secondly, the signal integrity in die-to-substrate vertical interconnection is simulated, comparing between 2.1D, 2.3D i-THOP® and the 2.5D silicon interposer. Finally, as for the power delivery point of view, power distribution network (PDN) impedance is compared between 2.1D and 2.3D i-THOP®.

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