Application of Alumina-Based Ceramic Paste for High-Temperature Electronics Packaging

2020 ◽  
Author(s):  
Ardalan Nasiri ◽  
Simon Ang
Keyword(s):  
High Temperature ◽  
Electronics Packaging ◽  
Bond Line ◽  
Alumina Powder ◽  
Nano Silica ◽  
High Temperature Electronics ◽  
Die Attach ◽  
Peak Broadening ◽  
Crystallite Sizes ◽  
Silica Ceramic

Abstract Alumina-based die attach and encapsulation for high-temperature (300oC to 500oC) electronic packaging were investigated. The alumina paste material comprises of aluminum dihydric phosphate as a binder and alumina powder as a filler with embedded nano aluminum nitride and nano-silica powders to promote its curing process, reduce its curing tension, and increase its bond shear strength. The chip-to-substrate bond strength was enhanced and met the MIL-STD-883 2019.9 requirements for die-attach assembly. Its encapsulation property was improved with fewer cracks compared to similar commercial ceramic encapsulants. The die-attach material and encapsulation properties tested at 500°C showed no defect or additional cracks. Thermal aging and thermal cycling were carried out on the samples. XPS analysis revealed a higher oxygen bonding percentage for the 10% nanosilica ceramic sample than the samples with no nano-silica. XRD peak broadening is largest for the 10% nano-silica ceramic which indicated smaller crystallite sizes. The smaller crystallite size for the 10% nanosilica sample introduces a larger microstrain to the alumina crystal structure. FTIR revealed the presence of alumina-silicate bonds on these samples with the largest amount present in the 10% nanosilica samples. Si-O and Al-O bonds were observed from FTIR on nanosilica samples especially the higher than 10% nanosilica samples. SEM and EDX results showed a uniform bond line for the 10% sample and uniform material distribution.

Diamond Heat Sinks For High Temperature Electronics: Simuilation, And Thermal Analysis

1995 ◽  
Vol 416 ◽  
Author(s):  
Nickolaos Strifas ◽  
Aris Christou
Keyword(s):  
Thermal Conductivity ◽  
Thermal Analysis ◽  
High Temperature ◽  
Thermal Resistance ◽  
Substrate Material ◽  
Heat Sinks ◽  
Substrate Thickness ◽  
High Temperature Electronics ◽  
Die Attach ◽  
Heat Sink Design

ABSTRACTperformance that can be achieved by utilizing a diamond heat - sink design which minimizes junction - to - case thermal resistance. Effects of the thermal conductivity of the substrate material, the thermal conductivity of the die attach material, the substrate thickness, and the die attach thickness onl Ihe thermal resistance are addressed. The results indicate that the temperature increase could be 3 to 4 times less with diamond heat-sinks when compared to other materials.

End of Life Failure Modes for Packaged SOI Devices for Signal Conditioning and Processing Applications

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000327-000334
Author(s):  
S T Riches ◽  
C Johnston ◽  
A Crossley ◽  
P Grant
Keyword(s):  
High Temperature ◽  
End Of Life ◽  
Failure Modes ◽  
Reliability Data ◽  
High Temperature Electronics ◽  
Die Attach ◽  
Aero Engine ◽  
Endurance Tests ◽  
Soi Devices

Silicon on Insulator (SOI) device technology has been shown to be capable of functioning satisfactorily at operating temperatures of >200°C. Most of the applications to date have required performance for short times (<2,000 hours) at the highest operating temperatures of up to 225°C in down-well drilling applications. There is interest in extending the endurance of high temperature electronics into aero-engine and other applications where a minimum 20 year operating life is stipulated. In order to gain confidence in high temperature electronics that can meet this requirement, accurate reliability data are needed and end of life failure modes need to be identified. Most of the reliability data on the high temperature endurance of the integrated circuit is generated with little consideration of the packaging technologies, whilst most of the reliability data pertinent to high temperature packaging technologies uses test pieces rather than devices, which limits any conclusions relating to long term electrical performance. This paper presents results of temperature storage and cycling endurance studies on SOI devices combined with high temperature packaging technologies relevant to signal conditioning and processing functions for sensors in down-well and aero-engine applications. The endurance studies have been carried out for up to 11,088 hours at 250°C, with functioning devices being tested periodically at room temperature, 125°C and 250°C and rapid thermal cycling from −40°C to +225°C. Different die attach and wire bond options have been included in the study and the performance of several functional blocks on the SOI device has been tracked over the endurance tests. The failure modes observed on completion of the endurance tests include die cracking and deterioration of the device bond pads accelerated due to degradation of some die attach materials. The routes to achieving stable long term performance of packaged devices at temperatures of 250°C will be outlined.

Improved sinterability of particles to substrates by surface modifications on substrate metallization

2019 ◽  
Vol 2019 (HiTen) ◽  
pp. 000066-000070 ◽  
Author(s):  
Sri Krishna Bhogaraju ◽  
Omid Mokhtari ◽  
Jacopo Pascucci ◽  
Fosca Conti ◽  
Gordon Elger
Keyword(s):  
High Temperature ◽  
High Power ◽  
Low Cost ◽  
Surface Modifications ◽  
Bonding Pressure ◽  
Light Emitting ◽  
High Temperature Electronics ◽  
Die Attach ◽  
N2 Atmosphere ◽  
Surface Modified

Abstract Sintering under pressure has been in the forefront of the research and development over the past decade as an alternative to high temperature soldering and die-attach bonding for high temperature electronics. However, high bonding pressure is a deterrent to mass industrialization due to the high costs involved in the design of special tooling and complex process control parameters. Further, it can cause device cracking, especially while working with sensitive high power optoelectronics devices (e.g. high power light emitting diodes). Therefore, alternatives to enhance sinterability are highly requested. Substrate metallization is observed to play an important role while sintering. An innovative low cost method to have nanostructured surface modifications on the substrates is realized and presented here. The method is applied to enhance sinterability of Cu particles to substrate. Shear tests on samples with surface modified substrates are promising with results of ca. 25 MPa, which is 24% better than sintering on unmodified bare Cu substrate. Sintering was enabled by in-house developed hybrid Cu paste under pressureless sintering conditions of 300°C, for 60 min, and under N2 atmosphere.

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