Improved sinterability of particles to substrates by surface modifications on substrate metallization

2019 ◽  
Vol 2019 (HiTen) ◽  
pp. 000066-000070 ◽  
Author(s):  
Sri Krishna Bhogaraju ◽  
Omid Mokhtari ◽  
Jacopo Pascucci ◽  
Fosca Conti ◽  
Gordon Elger

Abstract Sintering under pressure has been in the forefront of the research and development over the past decade as an alternative to high temperature soldering and die-attach bonding for high temperature electronics. However, high bonding pressure is a deterrent to mass industrialization due to the high costs involved in the design of special tooling and complex process control parameters. Further, it can cause device cracking, especially while working with sensitive high power optoelectronics devices (e.g. high power light emitting diodes). Therefore, alternatives to enhance sinterability are highly requested. Substrate metallization is observed to play an important role while sintering. An innovative low cost method to have nanostructured surface modifications on the substrates is realized and presented here. The method is applied to enhance sinterability of Cu particles to substrate. Shear tests on samples with surface modified substrates are promising with results of ca. 25 MPa, which is 24% better than sintering on unmodified bare Cu substrate. Sintering was enabled by in-house developed hybrid Cu paste under pressureless sintering conditions of 300°C, for 60 min, and under N2 atmosphere.

2019 ◽  
Vol 2019 (1) ◽  
pp. 000387-000392 ◽  
Author(s):  
Sri Krishna Bhogaraju ◽  
Omid Mokhtari ◽  
Jacopo Pascucci ◽  
Fosca Conti ◽  
Hiren R Kotadia ◽  
...  

Abstract High temperature power electronics based on wide-bandgap semiconductors have prominent applications, such as automotive, aircrafts, space exploration, oil/gas extraction, electricity distribution. Die-attach bonding process is an essential process in the realization of high temperature power devices. Here Cu offers to be a promising alternative to Ag, especially because of thermal and mechanical properties on par with Ag and a cost advantage by being a factor 100 cheaper than Ag. With the aim to achieve a low-pressure Cu sintering process, a low cost wet chemical etching process is developed to selectively etch Zn from brass to create nano-porous surface modifications to enhance sinterability, enabling sintering with low bonding pressure of 1MPa and at temperatures below 300°C. However, high tendency of Cu to oxidize poses a major challenge in realizing stable interconnects. For this purpose, in this contribution, we present the use of polyethylene-glycol 600 as reducing binder in the formulation of the Cu sintering paste. Finally, we propose a multi-pronged approach based on three crucial factors: surface-modified substrates, nanostructured surface modifications on micro-scale Cu-alloy particles and use of a reducing binder in the Cu particle paste.


2016 ◽  
Vol 2016 (HiTEC) ◽  
pp. 000226-000233
Author(s):  
Fang Yu ◽  
Jinzi Cui ◽  
Zhangming Zhou ◽  
R. Wayne Johnson ◽  
Michael C. Hamilton

Abstract With an increased demand for high power and high temperature electronics, Ag sintering paste has been considered a promising Pb-free die attach material candidate for these applications. A large amount of research has been performed investigating pressure and pressureless Ag sintering for die attach. In this work, passive component (chip resistor) attachment with Ag sintering was explored. Due to termination geometry differences between resistors and die, different processing procedures and parameters were developed. For PtAu terminated resistors, the mean shear force of as-built samples on thick film Ag metallized substrates was 90 N, but dropped to 18.6 N after 1500 hours at 300°C. Formation of a dense Ag layer near the PtAu resistor termination and a void region near the thick film metallization was observed in cross-sections after 1000 hours at 300°C. For PdAg terminated resistors with a plated Ni/Au finish, the initial shear force results were low due to Ag diffusion along Au metallization surface. For PdAg terminated resistors with Ag thick film substrates, the initial shear force was approximately 60 N and remained in the range of 50–70 N during aging at 300°C for 1500 hours. A new thick film metallization (Au+Ag) was developed to enable the use of thick film Au interconnect metallization.


2016 ◽  
Vol 13 (4) ◽  
pp. 155-162
Author(s):  
Fang Yu ◽  
Jinzi Cui ◽  
Zhangming Zhou ◽  
R. Wayne Johnson ◽  
Michael C. Hamilton

With an increased demand for high-power and high-temperature electronics, Ag sintering paste has been considered a promising Pb-free die-attach material candidate for these applications. Extensive research has been carried out investigating pressure and pressureless Ag sintering for die attach. In this work, passive component (chip resistor) attachment with Ag sintering was explored. Due to termination geometry differences between resistors and dies, different processing procedures and parameters were developed. For PtAu terminated resistors, the mean shear force of as-built samples on thick-film Ag metallized substrates was 90 N, but dropped to 18.6 N after 1,500 h at 300°C. Formation of a dense Ag layer near the PtAu resistor termination and a void region near the thick-film metallization was observed in cross sections after 1,000 h at 300°C. For PdAg terminated resistors with a plated Ni/Au finish, the initial shear force results were low due to Ag diffusion along Au metallization surface. For PdAg terminated resistors with Ag thick-film substrates, the initial shear force was ~60 N and remained in the range of 50–70 N during aging at 300°C for 1,500 h. A new thick-film metallization (Au + Ag) was developed to enable the use of thick-film Au interconnect metallization.


2010 ◽  
Vol 132 (3) ◽  
Author(s):  
Xin Li ◽  
Xu Chen ◽  
Guo-Quan Lu

As a solid electroluminescent source, white light emitting diode (LED) has entered a practical stage and become an alternative to replace incandescent and fluorescent light sources. However, due to the increasing integration and miniaturization of LED chips, heat flux inside the chip is also increasing, which puts the packaging into the position to meet higher requirements of heat dissipation. In this study, a new interconnection material—nanosilver paste is used for the LED chip packaging to pursue a better optical performance, since high thermal conductivity of this material can help improve the efficiency of heat dissipation for the LED chip. The bonding ability of this new die-attach material is evaluated by their bonding strength. Moreover, high-power LED modules connected with nanosilver paste, Sn3Ag0.5Cu solder, and silver epoxy are aged under hygrothermal aging and temperature cycling tests. The performances of these LED modules are tested at different aging time. The results show that LED modules sintered with nanosilver paste have the best performance and stability.


2011 ◽  
Vol 2011 (1) ◽  
pp. 000136-000141 ◽  
Author(s):  
Amanda Hartnett ◽  
Seth Homer ◽  
Donald Beck ◽  
Daniel Evans

High-power semiconductor devices, such as high-brightness Light Emitting Diodes (LEDs), must be mounted using a robust adhesive material to handle the temperature fluctuations generated by the chip and the mechanical stresses due to the coefficient of thermal expansion (CTE) mismatches between the die material and substrate it is mounted to. The selected material must also comply with current legislation restricting manufactured products containing numerous materials including some that were historically popular in HB LED applications due to environmental concerns. Eutectic gold-tin (AuSn) materials meet these requirements, and process recommendations for their implementation will be presented in this paper. Utilizing a Palomar Technologies die bonder, AuSn solder preforms and paste will be placed/dispensed and reflowed using a Pulsed Heat System (PHS). Evaluation methods comparing these means of eutectic die attach to a pre-plated AuSn die will be discussed. Technical generalizations will be detailed to explain the derivation of test methods as well as hypotheses of results.


2016 ◽  
Vol 37 (9) ◽  
pp. 1159-1165
Author(s):  
陈佳 CHEN Jia ◽  
李欣 LI Xin ◽  
孔亚飞 KONG Ya-fei ◽  
梅云辉 MEI Yun-hui ◽  
陆国权 LU Guo-quan

2010 ◽  
Vol 139-141 ◽  
pp. 1433-1437
Author(s):  
Kai Lin Pan ◽  
Jiao Pin Wang ◽  
Jing Liu ◽  
Guo Tao Ren

Heat dissipation and cost are the key issues for light-emitting diode (LED) packaging. In this paper, based on the thermal resistance network model of LED packaging, three-dimensional heat dissipation model of high power multi-chip LED packaging is developed and analyzed with the application of finite element method. Temperature distributions of the current multi-chip LED packaging model are investigated systematically under the different materials of the chip substrate, die attach, and/or different structures of the heat sink and fin. The results show that the junction temperature can be decreased effectively by increasing the height of the heat sink, the width of the fin, and the thermal conductivity of the chip substrate and die attach materials. The lower cost and higher reliability for LED source can be obtained through reasonable selection of materials and structure parameters of the LED lighting system.


2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Piaopiao He ◽  
Jinlong Zhang ◽  
Jianhua Zhang ◽  
Luqiao Yin

The reliability of high-power light-emitting-diode (LED) devices strongly depends on the die-attach quality because voids may increase junction temperature and total thermal resistance of LED devices. Die-attach material has a key role in the thermal management of high-power LED package by providing low-contact thermal resistance. Thermal and mechanical analyses were carried out by experiments and thermal simulation. The quantitative analysis results show that thermal resistance of die-attach layer (thermal resistance caused by die-attach material and voids in die-attach layer) plays an important role in total thermal resistance of high-power LED packaging according to the differential structure function of thermal transient characteristics. The increase of void fraction in die-attach layer causes the increases of thermal resistance of die-attach layer; the thermal resistance increased by 1.95 K/W when the void fraction increased to 62.45%. The voids also make an obvious influence on thermal stress and thermal strain of chip; the biggest thermal stress of chip was as high as 847.1 MPa compared to the 565.2 MPa when the void fraction increases from being void-free to 30% in the die-attach layer.


2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000073-000082
Author(s):  
Jinzi Cui ◽  
R. Wayne Johnson ◽  
Michael C. Hamilton

Nickel is a commonly used diffusion barrier for direct bond copper (DBC) substrates used in high temperature, high power applications. The Ni can be deposited by electroless or electrolytic plating and may be pure Ni, Ni:P, Ni:B or Ni:Co. The reactivity of these different Ni layers with AuGe and BiAgX® solder is explored. Specifically the reaction to form Ni-Ge intermetallics and NiBi3 during high temperature storage and the impact on die shear strength and failure mode are discussed.


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