Reliability Analysis of WLCSP Using Tie-Release Crack Prediction Finite Element Technique

2005 ◽  
Author(s):  
Chang-Chun Lee ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Fatigue Life ◽  
Solder Joint ◽  
Solder Joints ◽  
Wafer Level ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Prediction Technique ◽  
Packaging Structure

For the purpose of enhancing the solder joint reliability of a wafer level chip scaling package (WLCSP), the WLCSP adopted the familiar design structure where both the stress compliant layer with low elastic modulus and the dummy solder joints are considered as structural supports. However, the predicted fatigue life of the solder joints at the internal part of the packaging structure using the conventional procedures of finite element simulation are higher than under actual conditions as a result of the perfect bonding assumption in the modeling. In this research, in order to improve the thermo-mechanical reliability of the solder joints, a node tie-release crack prediction technique, based on non-linear finite element analysis (FEA), is developed and compared with the estimation of the solder joint reliability using conventional methodology. The predicted results of reliability, using the novel prediction technique, show a lower fatigue life of the solder joint than that when using conventional one when the fracture regions in the dummy solder joints are simulated under quasi-steady state. At the same time, the result of the thermal cycling test also shows good agreement with the simulated result when using the proposed node tie-release crack prediction analysis.

Inverse Derivation of Constants for the Constitutive Equation and Fatigue Model of Pb-Free Solder Joints Based on Experiment Results, Finite Element Simulation and Virtual Optimization Methodology

2012 ◽  
Author(s):  
Weidong Xie ◽  
Mudasir Ahmad
Keyword(s):  
Finite Element ◽  
Fatigue Life ◽  
Constitutive Equation ◽  
Solder Joint ◽  
Test Results ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Fatigue Model ◽  
End Use ◽  
Free Solder

Solder joint reliability of Pb-free ball grid array (BGA) components, one of the most commonly used microelectronic devices, is one of the major concerns in product development and qualification. Accelerated Thermal Cycling (ATC) testing, though very time consuming and costly, remains the most prevalent means to evaluate solder joint reliability under certain end-use conditions. Wherever the test results are not readily available, a fine-tuned and well-benchmarked modeling methodology is of significance in producing quick-turn judgments and risk assessments to expedite product development. The two most critical elements in simulating solder joint reliability are 1) the solder constitutive equations, which describe the solder creep behavior under different working conditions, and 2) the fatigue model which ties the damage index from finite element modeling together with the experimental results. In this study, a novel approach has been explored in which the constants of the constitutive equation and fatigue model for Sn-based Pb-free solder joints were derived inversely based on ATC results of a ceramic BGA test vehicle. In order to cover the typical end-use conditions of the targeted products, the test vehicle was assembled onto PCBs with two different thicknesses and then thermal cycled under three different temperature profiles. The basic idea was that all of the constants, both for the constitutive equation and the fatigue life prediction model, were initially given as a range. Then by utilizing modeFrontier®, a multi-objective optimization software, the finite-element model was coupled with the virtual optimization algorithm to derive simultaneously all the constants that yielded the best fatigue life predictions compared to the test results. To simplify the problem without compromising the generality, a hyperbolic sine creep constitutive equation and Coffin-Manson fatigue model were selected in the analysis. There were a total of 6 constants to be determined; the initial ranges of the constants were defined by fitting the creep experimental data for a variety of Sn-based solder materials. Available in other publications, the selected solder materials cover a wide range of both Ag and Cu content which therefore represent the typical behavior of the most commonly adopted solder materials by the industry. To reduce the computational cost and enable fast convergence of multiple-generation iterations required by the multiple objective optimization algorithms, a very-well benchmarked submodel has been employed. Furthermore, by utilizing ANSYS® high performance computing (HPC) capability and cloud computing, the computational time was reduced significantly. An overall good correlation was achieved between the fatigue life prediction using the constants derived by this approach and the test characteristic life.

Micro Solder Joint Reliability and Warpage Investigations of Extremely Thin Double-layered Stacked-chip Packaging

2021 ◽  
Author(s):  
Chang-Chun Lee ◽  
Kuo-Shu Kao ◽  
Hou-Chun Liu ◽  
Chia-Ping Hsieh ◽  
Tao-Chih Chang
Keyword(s):  
Solder Joint ◽  
Solder Joints ◽  
Chip Thickness ◽  
Temperature Cycling ◽  
Nonlinear Material ◽  
Element Analysis ◽  
Fatigue Lifetime ◽  
Joint Reliability ◽  
Packaging Structure ◽  
Ic Package

Abstract To overcome the limited operational speed for nano-scaled transistors, scaling electronic devices to small and thin packaging and high-density arrangements have become the technological mainstream in designing versatile packaging architectures. Among these, a promising candidate is the 3D-IC package due to its excellent capability of heterogeneous integration. However, sequential reliability is a troublesome concern given the complex packaging structure, especially for the assembly of micro solder joints. To address this issue, we propose a double-layered, thin stacked chip package under the application of temperature cycling load. The packaging warpage and creep impact of SnAg micro solder joints on their fatigue lifespan are examined separately. Nonlinear material/geometry finite element analysis is used on important designed factors, including the elastic modulus of underfill, chip thickness, and the radius and pitch of through silicon via (TSV). The simulated results indicate that the best fatigue lifetime of SnAg micro solder joint can be achieved at 10 µm of each chip thickness, 230 and 5 µm for TSV pitch and radius within the examined designed extent. Moreover, a hard underfill material requires consideration when the mounted chips thicken. Consequently, reliability significantly improves by dispersing thermo-mechanical stress/strain of the SnAg microjoints to neighboring underfill and related packaging components, especially for large TSV array spacing.

Parameterized Modeling of Thermomechanical Reliability for CSP Assemblies

2003 ◽  
Vol 125 (4) ◽  
pp. 498-505 ◽  
Author(s):  
Bart Vandevelde ◽  
Eric Beyne ◽  
Kouchi (G.Q.) Zhang ◽  
Jo Caers ◽  
Dirk Vandepitte ◽  
...  
Keyword(s):  
Finite Element ◽  
Solder Joint ◽  
Empirical Model ◽  
Prediction Models ◽  
Solder Joints ◽  
Coefficient Of Thermal Expansion ◽  
Solder Joint Reliability ◽  
Joint Geometry ◽  
Joint Reliability ◽  
Area Array

Finite element modeling is widely used for estimating the solder joint reliability of electronic packages. In this study, the electronic package is a CSP mounted on a printed circuit board (PCB) using an area array of solder joints varying from 5×4 up to 7×7. An empirical model for estimating the reliability of CSP solder joints is derived by correlating the simulated strains to thermal cycling results for 20 different sample configurations. This empirical model translates the inelastic strains calculated by nonlinear three-dimensional (3D) finite element simulations into a reliability estimation (N50% or N100 ppm). By comparing with the results of reliability tests, it can be concluded that this model is accurate and consistent for analyzing the effect of solder joint geometry. Afterwards, parameter sensitivity analysis was conducted by integrating a design of experiment (DOE) analysis with the reliable solder fatigue prediction models, following the method of simulation-based optimization. Several parameters are analyzed: the PCB parameters (elastic modulus, coefficient of thermal expansion, thickness), the chip dimensions (area array configuration), and the parameters defining the solder joint geometry (substrate and chip pad diameter, solder volume). The first study analyzes how the solder joint geometry influences the CSP reliability. A second study is a tolerance analysis for six parameters. These parameters can have a tolerance (=accuracy) of their nominal value, and it is shown that these small tolerances can have a significant influence on the solder joint reliability.

A Novel Prediction Technique for Interfacial Crack Growth of Electronic Interconnect

2006 ◽  
Vol 326-328 ◽  
pp. 533-536
Author(s):  
Chang Chun Lee ◽  
Hsiao Tung Ku ◽  
Chien Chia Chiu ◽  
Kuo Ning Chiang
Keyword(s):  
Fatigue Life ◽  
Crack Growth ◽  
Solder Joints ◽  
Interfacial Crack ◽  
Actual Condition ◽  
Wafer Level ◽  
Material Interface ◽  
Element Analysis ◽  
Prediction Technique ◽  
Reliability Of Solder Joints

The predicted fatigue life of packaging structures using conventional procedures of finite element analysis (FEA) would be higher than an actual condition as a result of the perfect bonding interface assumed in the modeling. Actually, the crack extension of the solder joints along with the bi-material interface during the thermal cycling test had been observed. And, the crack models with an assumed crack length had widely adopted which only responded to the stress distribution at that moment instead of considering the effect of the whole stress history on the crack advancement. For this reason, a node tie-release crack prediction technique integrated with a nonlinear FEA was established in this research to further estimation for the thermo-mechanical reliability of solder joints. To proof our proposed technique, a double-layer wafer level chip-scaling package (DLWLCSP) was implemented as a testing vehicle to demonstrate the difference between the solder joint reliability, which was compared to the application of conventional FEA. Combined with the fracture criterion, the predicted result of using the present technique shown a lower fatigue life of solder joints than another, which using conventional one when the phenomenon of crack growth in dummy solder joints were considered. Finally, the actual experimental test showed the similar results as presented tie-release crack prediction analysis.

Design and Reliability Analysis of Wafer Level Package With Bubble-Like Buffer Layer

2003 ◽  
Author(s):  
Chang-Chun Lee ◽  
Kuo-Ning Chiang
Keyword(s):  
Solder Joint ◽  
Buffer Layer ◽  
Chip Thickness ◽  
Buffer Layers ◽  
Wafer Level ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Compliant Layer ◽  
Wafer Level Package

In order to enhance the wafer level package (WLP, Figure 1) reliability for larger chip size, many different kinds of WLP have been adopted, all have a compliant layer under the pads have to relieve the thermal stress of the solder joint. Usually, the solder joint reliability is enhanced with the increase of the thickness of the compliant layer. However, the fabrication processes of the WLP restrict the thickness of the compliant layer. With that in mind this research proposed a novel WLP package with bubble-like buffer layer (Figure 2) which is composed of a bubble-like plate and a buffer layer between the chip and the solder joint. The main goal of this research was to study the effects of the geometric dimensions and material properties of the bubble-like layer on the reliability of the WLP. For the parametric analysis purpose, a 2-D nonlinear finite element analysis for the proposed WLP was conducted. The results revealed that both the bubble-like plate and the buffer layer provide excellent compliant effects. However, the buffer layer has a more significant effect on enhancing the solder joint reliability. Also, for a WLP with buffer structure, the effect of the chip thickness on the reliability could be significantly reduced. In addition, the difference between the filled and non-filled buffer layers also affected the reliability of the solder joint. The results revealed that the WLP with the buffer layer and the no-fill bubble-like plate had the better reliability.

Estimating the Vibration Fatigue Life of Quad Leaded Surface Mount Components

1993 ◽  
Vol 115 (2) ◽  
pp. 195-200 ◽  
Author(s):  
D. B. Barker ◽  
Y. S. Chen ◽  
A. Dasgupta
Keyword(s):  
Finite Element ◽  
Fatigue Life ◽  
Solder Joint ◽  
Finite Element Modeling ◽  
Stress Analysis ◽  
Empirical Equation ◽  
Solder Joint Reliability ◽  
Surface Mount ◽  
Joint Reliability ◽  
Vibration Fatigue

This paper discusses the assumptions and details of the fatigue life calculations required to predict the fatigue life of quad leaded surface mount components operating in a vibration environment. A simple approximate stress analysis is presented that does not require complex finite element modeling, nor does it reduce the problem to a simple empirical equation or rule of thumb. The goal of the new method is to make PWB vibration solder joint reliability information available to the designer as early as possible and in an easily understood and implemented manner.

Strategies for Improving Reliability of Solder Joints on Power Semiconductor Devices

2003 ◽  
Author(s):  
Guo-Quan Lu ◽  
Xingsheng Liu ◽  
Sihua Wen ◽  
Jesus Noel Calata ◽  
John G. Bai
Keyword(s):  
Finite Element ◽  
Solder Joint ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Solder Joints ◽  
Mechanical Stresses ◽  
Flexible Substrates ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Reliability Of Solder Joints

There has been a significant research effort on area-array flip-chip solder joint technology in order to reduce package footprint, enhance current handling capability, and improve heat dissipation. However, there is a lingering concern over cyclic fatigue of solder alloys by thermo-mechanical stresses arising from mismatched thermal expansion coefficients of expansion among the various components of the package. In this paper, some strategies taken to improve the reliability of solder joints on power devices in single-device and multi-chip packages are presented. A strategy for improving solder joint reliability by adjusting solder joint geometry, underfilling and utilization of flexible substrates is discussed with emphasis on triple-stacked solder joints that resemble the shape of an hourglass. The hourglass shape relocates the highest inelastic strain away from the weaker interface with the chip to the bulk region of the joint while the underfill provides a load transfer from the joints. Flexible substrates can deform to relieve thermo-mechanical stresses. Thermal cycling data show significant improvements in reliability when these techniques are used. The design, testing, and finite-element analyses of an interconnection structure, termed the Dimple-Array Interconnect (DAI), for improving the solder joint reliability is also presented. In the DAI structure, a solder is used to join arrays of dimples pre-formed on a metal sheet onto the bonding pads of a device. Finite-element thermo-mechanical analyses and thermal cycling data show that the dimple-array solder joints are more fatigue-resistant than the conventional barrel-shaped solder joints in flip-chip IC packages.

scholarly journals Prediction of Thermal Fatigue Life of Lead-Free BGA Solder Joints by Finite Element Analysis

2001 ◽  
Vol 42 (5) ◽  
pp. 809-813 ◽  
Author(s):  
Young-Eui Shin ◽  
Kyung-Woo Lee ◽  
Kyong-Ho Chang ◽  
Seung-Boo Jung ◽  
Jae Pil Jung
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Fatigue Life ◽  
Thermal Fatigue ◽  
Solder Joints ◽  
Lead Free ◽  
Element Analysis ◽  
Thermal Fatigue Life
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