Design and Reliability Analysis of Wafer Level Package With Bubble-Like Buffer Layer

2003 ◽  
Author(s):  
Chang-Chun Lee ◽  
Kuo-Ning Chiang
Keyword(s):  
Solder Joint ◽  
Buffer Layer ◽  
Chip Thickness ◽  
Buffer Layers ◽  
Wafer Level ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Compliant Layer ◽  
Wafer Level Package

In order to enhance the wafer level package (WLP, Figure 1) reliability for larger chip size, many different kinds of WLP have been adopted, all have a compliant layer under the pads have to relieve the thermal stress of the solder joint. Usually, the solder joint reliability is enhanced with the increase of the thickness of the compliant layer. However, the fabrication processes of the WLP restrict the thickness of the compliant layer. With that in mind this research proposed a novel WLP package with bubble-like buffer layer (Figure 2) which is composed of a bubble-like plate and a buffer layer between the chip and the solder joint. The main goal of this research was to study the effects of the geometric dimensions and material properties of the bubble-like layer on the reliability of the WLP. For the parametric analysis purpose, a 2-D nonlinear finite element analysis for the proposed WLP was conducted. The results revealed that both the bubble-like plate and the buffer layer provide excellent compliant effects. However, the buffer layer has a more significant effect on enhancing the solder joint reliability. Also, for a WLP with buffer structure, the effect of the chip thickness on the reliability could be significantly reduced. In addition, the difference between the filled and non-filled buffer layers also affected the reliability of the solder joint. The results revealed that the WLP with the buffer layer and the no-fill bubble-like plate had the better reliability.

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

2008 ◽  
Vol 48 (4) ◽  
pp. 602-610 ◽  
Author(s):  
Xiaowu Zhang ◽  
Vaidyanathan Kripesh ◽  
T.C. Chai ◽  
Teck Chun Tan ◽  
D. Pinjala
Keyword(s):  
Solder Joint ◽  
Reliability Analysis ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Fine Pitch ◽  
Board Level ◽  
Wafer Level Package

Solder joint reliability of a polymer reinforced wafer level package

2002 ◽  
Vol 42 (12) ◽  
pp. 1837-1848 ◽  
Author(s):  
Deok-Hoon Kim ◽  
Peter Elenius ◽  
Michael Johnson ◽  
Scott Barrett
Keyword(s):  
Solder Joint ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Wafer Level Package

Reliability Analysis of WLCSP Using Tie-Release Crack Prediction Finite Element Technique

2005 ◽  
Author(s):  
Chang-Chun Lee ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Fatigue Life ◽  
Solder Joint ◽  
Solder Joints ◽  
Wafer Level ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Prediction Technique ◽  
Packaging Structure

For the purpose of enhancing the solder joint reliability of a wafer level chip scaling package (WLCSP), the WLCSP adopted the familiar design structure where both the stress compliant layer with low elastic modulus and the dummy solder joints are considered as structural supports. However, the predicted fatigue life of the solder joints at the internal part of the packaging structure using the conventional procedures of finite element simulation are higher than under actual conditions as a result of the perfect bonding assumption in the modeling. In this research, in order to improve the thermo-mechanical reliability of the solder joints, a node tie-release crack prediction technique, based on non-linear finite element analysis (FEA), is developed and compared with the estimation of the solder joint reliability using conventional methodology. The predicted results of reliability, using the novel prediction technique, show a lower fatigue life of the solder joint than that when using conventional one when the fracture regions in the dummy solder joints are simulated under quasi-steady state. At the same time, the result of the thermal cycling test also shows good agreement with the simulated result when using the proposed node tie-release crack prediction analysis.

Solder Joint Reliability Modeling of WLP and FOWLP with Crack Path Evaluation Method under Thermal Cycling

2020 ◽  
Vol 2020 (1) ◽  
pp. 000001-000004
Author(s):  
Dae-Suk Kim ◽  
Karthikeyan Dhandapani
Keyword(s):  
Solder Joint ◽  
Thermal Cycling ◽  
Crack Path ◽  
Path Selection ◽  
Circuit Board ◽  
Critical Element ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Wafer Level Package

Abstract An updated solder joint reliability (SJR) modeling methodology under thermal cycling (TC) is proposed and implemented for the diagonal solder crack path case as well as the SJR correlation of wafer-level package (WLP) and fan-out wafer-level package (FOWLP) data, which have the conventional solder failure mode around the under-bump metallization (UBM). First, two critical element layers near by the UBM layer and the printed circuit board (PCB) Cu pad are defined as the percentage of the total solder height in order to differentiate the critical element size around the UBM and the PCB Cu pad. Secondly, a crack path evaluation (CPE) method is developed for the gradual selection of the elements from the highest creep strain energy density (SED) value up to the predefined volume. The conventional solder crack path at the package interface or the diagonal solder crack path can be analyzed depending on the package technology because the critical solder elements are selected depending on the SED level and the failure path. The proposed SJR modeling method successfully demonstrates the diagonal solder crack path selection and further improves the SJR correlation of WLP and FOWLP.

Solder Joint Reliability Study for Wafer Level Packages on Flexible and Rigid Boards

2013 ◽  
Vol 2013 (1) ◽  
pp. 000039-000044
Author(s):  
Gary Gu ◽  
Jon Chadwick ◽  
Daniel Jin
Keyword(s):  
Solder Joint ◽  
Parametric Design ◽  
Low Cost ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Conformal Coating ◽  
Joint Reliability ◽  
Chip Size ◽  
The Right ◽  
Elastic Plastic Materials

Applications of Wafer Level Packages (WLPs) have shown tremendous growth in the rapid developing smartphones and other portable electronic devices. The technology trends lead to smaller chip size, low cost, and more integrated functions, but also face higher reliability requirements due to the reduced number of solder bumps as well as smaller bump size and height. New assembly technologies such as flexible phone board and conformal coating also brought up new thermo-mechanical reliability challenges. Based on 3D finite element modeling, the current studies focus on solder joint reliability of WLPs and compared between flex based and traditional rigid based WLP assemblies. Conformal coated and underfilled WLPs as well as some bump parameters are also studied. The parametric studies were carried out in ANSYS and all models were created by using APDL (ANSYS Parametric Design Language) scripts. Each simulation starts from stress free status set at solder reflow temperature and were subjected to thermal cyclic load between −40 and +125°C with ramp and dwell time. Creep strain was considered for solder alloys and kinematic plastic hardening was considered for other elastic-plastic materials. The solder fatigue life is estimated by using modified Coffin-Manson equation and was compared with available thermal cycling test data. The results show that underfill is still the most effective option and conformal coating can play an important role if the right material is selected. Bump parameters such as height, which have certain effects on the solder reliability on WLP-on-Rigid, have limited impact on WLP-on-Flex assembly.

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