Package Tilt Prediction Using Surface Evolver

2007 ◽  
Author(s):  
Benjie B. Hornales ◽  
Erwin Ian V. Almagro
Keyword(s):  
Solder Joint ◽  
Visual Basic ◽  
Command Line ◽  
Surface Evolver ◽  
Joint Geometry ◽  
Joint Prediction ◽  
Joint Shape ◽  
User Friendly ◽  
Board Level ◽  
Data Surface

In board level package mounting process, many parameters will influence the final joint shape including the package stand-off height. If the stand-off height of solder joints at opposite ends does not equal, package tilting will occur. As a proactive measure to ascertain no tilting issues for newly develop packages, a methodology of predicting package tilting for BGA is developed using an energybased simulation model with surface evolver. The solder joint prediction model developed by Brakke proved to be very useful in predicting solder joint geometry after reflow and it will also be used to predict package tilting for BGA during board level mounting. This paper will discuss the capability of Surface Evolver in predicting solder joint geometry like solder ball height and diameter, and solder joint height. Then it moves on to discuss the methodology in using the same tool in predicting package tilting in board mounting process. It will be shown that the result of the surface evolver is well within the experimental data. Surface evolver program requires a command line input programming which is not very user-friendly, so a user interface was created using Visual Basic® 6 so that the engineer will only need to input relevant parameters into the program and command encoding is done automatically.

Influence Of Solder Joint Shape On The Thermo-Mechanical Reliability Of CSP's

2004 ◽  
Vol 1 (2) ◽  
pp. 53-63 ◽  
Author(s):  
Co van Veen ◽  
Bart Vandevelde ◽  
Eric Beyne
Keyword(s):  
Solder Joint ◽  
Force Constant ◽  
Local Stress ◽  
Simulation Software ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Surface Evolver ◽  
Joint Shape ◽  
Profile Estimation ◽  
Analytical Expressions

Not only the stand-off height but also the shape of a solder joint has a strong influence on the joint reliability under temperature cycling. The shape determines the size of the local stress and strain concentrations. It is therefore very important to know well the joint shape after reflow. In a previous paper closed analytical expressions were derived for liquid bump shapes, as a function of pad size and bump height [1]. The bump deformation as a function of the chip weight could be derived from the force constant. In the present paper closed analytical expressions are derived for the force constant for liquid bumps having unequal spherical pad sizes. It turns out that the force constant for compression can be optimized as a function of the ratio of those pad sizes. The shape of the bump and especially the contact angle is of interest for modeling activities where geometrical effects do play a role. Furthermore from the variation in bumps heights on a chip an estimate can be made of the tilt of the chip after assembly. The solder profile estimation by the analytical expressions is validated by experimental results. Also a comparison with the solder profile estimation by the simulation software Surface Evolver is done. Both comparisons showed that the analytical estimation of the standoff height is very good as long as the gravitation energy contributed by the chip weight is less than 10% of the total energy. Finally, an example is shown where the analytical model and Surface Evolver are the geometrical input for a finite element model. The example considers a CSP assembled at both sides of the printed circuit board.

Improving WLCSP Reliability Through Solder Joint Geometry Optimization

2013 ◽  
Vol 2013 (1) ◽  
pp. 000546-000550 ◽  
Author(s):  
Boyd Rogers ◽  
Chris Scanlan
Keyword(s):  
Solder Joint ◽  
Thermal Cycling ◽  
Printed Circuit Board ◽  
Geometry Optimization ◽  
Circuit Board ◽  
Wafer Level ◽  
Joint Geometry ◽  
Chip Scale Package ◽  
Large Platform ◽  
Board Level

The effects of solder joint geometry on wafer-level chip-scale package reliability have been studied both through simulations and board level reliability testing. In reliability tests on a 3.9×3.9mm2 die, an enhancement of nearly 2× in thermal cycling reliability was achieved by optimizing the solder joint and under-bump pad stack. In particular, undersizing the printed circuit board pad to produce a more spherical solder joint and reducing the polymer via size under the bump appear to be very important for improving thermal cycling results. Data collected here shows that joint geometry changes can be implemented without compromising drop performance. Methods learned were applied to the qualification of a 6.0×6.0mm2 die, a large platform for WLCSP applications.

Experimental Investigation by Speckle Interferometry of Solder Joint Failure Under Thermomechanical Load Aggravated by Boundary Conditions at Board Level

2012 ◽  
Vol 134 (4) ◽  
Author(s):  
D. N. Borza ◽  
I. T. Nistea
Keyword(s):  
Solder Joint ◽  
Fundamental Frequency ◽  
Printed Circuit Board ◽  
Speckle Interferometry ◽  
Circuit Board ◽  
Joint Failure ◽  
Printed Circuit ◽  
Out Of Plane ◽  
Fringe Patterns ◽  
Board Level

Reliability of electronic assemblies at board level and solder joint integrity depend upon the stress applied to the assembly. The stress is often of thermomechanical or of vibrational nature. In both cases, the behavior of the assembly is strongly influenced by the mechanical boundary conditions created by the printed circuit board (PCB) to casing fasteners. In many previously published papers, the conditions imposed to the fasteners are mostly aiming at an increase of the fundamental frequency and a decrease of static or dynamic displacement values characterizing the deformation. These conditions aim at reducing the fatigue in different parts of these assemblies. In the photomechanics laboratory of INSA Rouen, the origins of solder joint failure have been investigated by means of full-field measurements of the flexure deformation induced by vibrations or by forced thermal convection. The measurements were done both at a global level for the whole printed circuit board assembly (PCBA) and at a local level at the solder joints where failure was reported. The experimental technique used was phase-stepped laser speckle interferometry. This technique has a submicrometer sensitivity with respect to out-of-plane deformations induced by bending and its use is completely nonintrusive. Some of the results were comforted by comparison with a numerical finite elements model. The experimental results are presented either as time-average holographic fringe patterns, as in the case of vibrations, or as wrapped phase patterns, as in the case of deformation under thermomechanical stress. Both types of fringe patterns may be processed so as to obtain the explicit out-of-plane static deformation (or vibration amplitude) maps. Experimental results show that the direct cause of solder joint failure may be a high local PCB curvature produced by a supplementary fastening screw intended to reduce displacements and increase fundamental frequency. The curvature is directly responsible for tensile stress appearing in the leads of a large quad flat pack (QFP) component and for shear in the corresponding solder joints. The general principle of increasing the fundamental frequency and decreasing the static or dynamic displacement values has to be checked against the consequences on the PCB curvature near large electronic devices having high stiffness.

Use-Conditions-Based Board Level Shock Test Development for Handheld Components

2004 ◽  
Author(s):  
Shubhada Sahasrabudhe ◽  
Vinayak Pandey ◽  
Betty Phillips ◽  
Kang Joon Lee ◽  
Lei Mercado
Keyword(s):  
Solder Joint ◽  
Cell Phone ◽  
Standardized Test ◽  
Test Development ◽  
Failure Mechanisms ◽  
Reliability Test ◽  
Shock Test ◽  
Board Level ◽  
Test Repeatability

For handheld electronic applications such as cell phones and Personal Digital Assistants (PDAs), drop/impact could result in considerable flexure of the printed circuit board (PCB) mounted inside the cell phone housing. The mechanical stresses may cause electrical failure of the components, with typical failure mechanisms of board trace cracking, solder joint fatigue, and solder pad cracking. A standardized test needs to be developed to assess reliability of handheld components subjected to impacts. The test should facilitate high volume testing, maximize margin for safety factors, and capture the failure mechanisms in the field environment. To develop the reliability test using use conditions based reliability methodology, comprehensive characterization of the mechanical field stresses during end use conditions is particularly essential. This paper discusses complete cell phone drop characterization along with the shock test developed to test the components subjected to such drops. Novel fixtures have been designed to simulate free fall of the cell phone in specific orientations. After the complete characterization of cell phone use conditions, board level shock test has been selected to assess component reliability. Test repeatability, number of components on the test board, and layout of the components are some of the factors considered during the board level shock test development. Several parameters like screw and washer designs, torque have been studied to yield excellent test repeatability. Nonlinear Dynamic Finite Element Simulation has been performed to provide more insight into the interaction of the bending modes and its impact on the solder joint failures. This paper demonstrates the process of understanding use conditions, developing reliability tests, validating test results and driving industry standards.

Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

2011 ◽  
Vol 423 ◽  
pp. 26-30
Author(s):  
S. Assif ◽  
M. Agouzoul ◽  
A. El Hami ◽  
O. Bendaou ◽  
Y. Gbati
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Dynamic Responses ◽  
Circuit Board ◽  
Joint Stress ◽  
Printed Circuit ◽  
Increasing Demand ◽  
Improved Model ◽  
Board Level

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

Board Level Reliability of Solder Joint with a Low CTE PCB

2019 ◽  
Vol 44 (1) ◽  
pp. 975-983 ◽  
Author(s):  
Kyoungmoo Harr ◽  
Chang-Bae Lee ◽  
Yoon-Su Kim ◽  
Seungwook Park ◽  
Jin-Gu Kim ◽  
...  
Keyword(s):  
Solder Joint ◽  
Board Level ◽  
Board Level Reliability
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