State-of-the-Art and Trends in Through-Silicon Via (TSV) and 3D Integrations

Author(s):  
John H. Lau

3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general the TSV (through-silicon via) separates 3D IC packaging from 3D IC integration and 3D Si integration since the latter two use TSV but 3D IC packaging does not. TSV (with a new concept that every chip could have two surfaces with circuits) is the focus of this investigation. State-of-the-art, key differences, trends of these three technologies, and a 3D integration roadmap are presented.

2014 ◽  
Vol 136 (4) ◽  
Author(s):  
John H. Lau

3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed.


2016 ◽  
Vol 59 ◽  
pp. 84-94 ◽  
Author(s):  
Hsien-Chie Cheng ◽  
Tzu-Chin Huang ◽  
Po-Wen Hwang ◽  
Wen-Hwa Chen

2009 ◽  
Vol 27 (3) ◽  
pp. 4-9
Author(s):  
Seung-Min Hyun ◽  
Chang-Woo Lee

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