Pb-Free Thin Small Outline Package (TSOP) Board Level Reliability Study

2009 ◽  
Author(s):  
Weidong Xie ◽  
Kuo-Chuan Liu ◽  
Mark Brillhart
Keyword(s):  
Solder Joint ◽  
Coefficient Of Thermal Expansion ◽  
Circuit Board ◽  
Solder Paste ◽  
Eutectic Solder ◽  
Qualification Testing ◽  
Free Solder ◽  
Board Level ◽  
The Impact

Thin Small Outline Package (TSOP) are one of the most commonly used surface mount components due to its low overall cost. Traditionally leadframe packages such as TSOP or Quad Flat Package (QFP) are less of a concern (if assembled with SnPb eutectic solder paste) about their long term reliability and often exempted from board level qualification testing as the mechanical compliance of metal leads mitigate the stresses due to the Coefficient of Thermal Expansion (CTE) mismatch between the package and Print Circuit Board (PCB). Therefore more attention has been put on the solder joint reliability of Pb-free Ball Grid Array (BGA) packages over leadframe packages while the industry is moving away from SnPb eutectic solder materials to meet RoHS regulatory requirements. The authors have observed that TSOPs if assembled with Pb-free solder materials could fail at very early stages during qualification testing (in some case as early as 300 cycles under standard 0°C to 100°C thermal cycling). Since most Pb-free solder materials such as SnAgCu are mechanically more rigid than SnPb eutectic solder material, higher stresses are expected be induced in solder joints during temperature excursions. Pb-free solder materials’ wicking behavior may also contribute to the early failures. In this study, long term reliability of a flash memory TSOP has been investigated. These tested TSOPs, assembled on 93mil-thick PCBs with SAC305 paste, are of two configurations: one with single die and the other with stacked quadruple dies. Some test vehicles have been thermally aged under four different thermal aging conditions to study the aging effect on Pb-free solder joint life. Finite element analysis (FEA) modeling has also been employed to further investigate the impact of other parameters such as die size, package size, and the number of dies that being stacked inside one package.

Modeling and Simulation of PCB Assembly under Board-Level Drop Impact

2010 ◽  
Vol 34-35 ◽  
pp. 451-455
Author(s):  
Fang Liu ◽  
Guang Meng
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Fe Model ◽  
Fe Method ◽  
Acceleration Pulse ◽  
Pcb Assembly ◽  
Free Solder ◽  
Board Level

Finite element (FE) method is an efficient and power tool, and is adopted to analyze dynamic response of printed circuit board (PCB) assembly. First, FE model of PCB assembly was established. Second, the dynamic behaviors of ball gird array (BGA) lead-free solder joint were obtained when the PCB assembly was subjected to a half-sine acceleration pulse. Results show that the maximum tensile stresses occur at solder joints located at the four outermost corners of BGA and solder joints at outermost corners are the most vulnerable to crack. In addition, it can be found during FE analysis that the solder joint reliability can be enhanced as the PCB damping increases and input acceleration level reduces.

Experimental approach to thermal conductivity of macro solder joints with voids

2019 ◽  
Vol 31 (3) ◽  
pp. 181-191 ◽  
Author(s):  
Maciej Sobolewski ◽  
Barbara Dziurdzia
Keyword(s):  
Thermal Conductivity ◽  
Solder Joint ◽  
Solder Joints ◽  
Copper Plate ◽  
Circuit Board ◽  
Solder Paste ◽  
Reflow Soldering ◽  
Content Type ◽  
Copper Cylinder ◽  
The Impact

Purpose The purpose of the paper is to experimentally evaluate the impact of voids on thermal conductivity of a macro solder joint formed between a copper cylinder and a copper plate by using reflow soldering. Design/methodology/approach A model of a surface mount device (SMD) was developed in the shape of a cylinder. A copper plate works as a printed circuit board (PCB). The resistor was connected to a power supply and the plate was cooled by a heat sink and a powerful fan. A macro solder joint was formed between a copper cylinder and a copper plate using reflow soldering and a lead-free solder paste SAC305. The solder paste was printed on a plate through stencils of various apertures. It was expected that various apertures of stencils will moderate the various void contents in solder joints. K-type thermocouples mounted inside cylinders and at the bottom of a plate underneath the cylinders measured the temperature gradient on both sides of the solder joint. After finishing the temperature measurements, the cylinders were thinned by milling to thickness of about 2 mm and then X-ray images were taken to evaluate the void contents. Finally the tablets were cross-sectioned to enable scanning electron microscopy (SEM) observations. Findings There was no clear dependence between thermal conductivity of solder joints and void contents. The authors state that other factors such as intermetallic layers, microcracks, crystal grain morfologyof the interface between the solder and the substrate influence on thermal conductivity. To support this observation, further investigations using metallographic methods are required. Originality/value Results allow us to assume that the use of SAC305 alloy for soldering of components with high thermal loads is risky. The common method for thermal balance calculation is based on the sum of serial thermal resistances of mechanical compounds. For these calculations, solder joints are represented with bulk SAC305 thermal conductivity parameters. Thermal conductivity of solder joints for high density of thermal energy is much lower than expected. Solder joints’ structure is not fully comparable with bulk SAC305 alloy. In experiments, the average value of the solder joint conductivity was found to be 8.1 W/m·K, which is about 14 per cent of the nominal value of SAC305 thermal conductivity.

Influence of Intermetallic Characteristics on the Solder Joint Strength of Halogen-Free Printed Circuit Board Assembly

2011 ◽  
Vol 133 (2) ◽  
Author(s):  
Hung-Jen Chang ◽  
Jung-Hua Chou ◽  
Tao-Chih Chang ◽  
Chau-Jie Zhan ◽  
Min-Hsiung Hon ◽  
...  
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Solder Paste ◽  
Sac305 Solder ◽  
Printed Circuit ◽  
Pull Strength ◽  
Free Solder ◽  
Halogen Free ◽  
Electroless Ni

Five halogen-free (HF) dummy plastic ball grid array (PBGA) components with daisy-chains and Sn4.0Ag0.5Cu (SAC405) Pb-free solder balls were assembled on a HF high density interconnection (HDI) printed circuit board (PCB) using Sn1.0Ag0.5Cu (SAC105) and Sn3.0Ag0.5Cu (SAC305) Pb-free solder pastes, respectively. The above compositions were in weight percent. The assemblies were then experienced to moisture sensitive level testing with three times reflow at a peak temperature of 260 °C; no delamination was found present in both the component and PCB laminates. The microstructure showed that the utilization of SAC105 solder paste was beneficial in refining the Ag3Sn intermetallic compound (IMC) within the solder joint and the intermetallic layers formed at various interfaces with different Ni contents and thicknesses due to different metal finishes. The IMC spalling was found at the BGA-side interface within the solder joints formed with SAC105 solder paste but not discovered within the ones made of SAC305 solder paste. The pull strength of the solder joint formed with SAC305 solder paste was always higher than that made from SAC105 no matter on Cu or electroless Ni. Moreover, the fracture was found at the interface between the Cu foil and epoxy in the halogen-free test device. Numerical analysis showed that the thickness of IMC layer dominated the pull strength of the solder joint because the Z-axial normal stress applied to the solder joints formed with Cu and electroless Ni were 752.0 and 816.6 MPa, respectively, and a thicker IMC layer was beneficial to provide a higher pull strength of solder joint.

Experimental Investigation by Speckle Interferometry of Solder Joint Failure Under Thermomechanical Load Aggravated by Boundary Conditions at Board Level

2012 ◽  
Vol 134 (4) ◽  
Author(s):  
D. N. Borza ◽  
I. T. Nistea
Keyword(s):  
Solder Joint ◽  
Fundamental Frequency ◽  
Printed Circuit Board ◽  
Speckle Interferometry ◽  
Circuit Board ◽  
Joint Failure ◽  
Printed Circuit ◽  
Out Of Plane ◽  
Fringe Patterns ◽  
Board Level

Reliability of electronic assemblies at board level and solder joint integrity depend upon the stress applied to the assembly. The stress is often of thermomechanical or of vibrational nature. In both cases, the behavior of the assembly is strongly influenced by the mechanical boundary conditions created by the printed circuit board (PCB) to casing fasteners. In many previously published papers, the conditions imposed to the fasteners are mostly aiming at an increase of the fundamental frequency and a decrease of static or dynamic displacement values characterizing the deformation. These conditions aim at reducing the fatigue in different parts of these assemblies. In the photomechanics laboratory of INSA Rouen, the origins of solder joint failure have been investigated by means of full-field measurements of the flexure deformation induced by vibrations or by forced thermal convection. The measurements were done both at a global level for the whole printed circuit board assembly (PCBA) and at a local level at the solder joints where failure was reported. The experimental technique used was phase-stepped laser speckle interferometry. This technique has a submicrometer sensitivity with respect to out-of-plane deformations induced by bending and its use is completely nonintrusive. Some of the results were comforted by comparison with a numerical finite elements model. The experimental results are presented either as time-average holographic fringe patterns, as in the case of vibrations, or as wrapped phase patterns, as in the case of deformation under thermomechanical stress. Both types of fringe patterns may be processed so as to obtain the explicit out-of-plane static deformation (or vibration amplitude) maps. Experimental results show that the direct cause of solder joint failure may be a high local PCB curvature produced by a supplementary fastening screw intended to reduce displacements and increase fundamental frequency. The curvature is directly responsible for tensile stress appearing in the leads of a large quad flat pack (QFP) component and for shear in the corresponding solder joints. The general principle of increasing the fundamental frequency and decreasing the static or dynamic displacement values has to be checked against the consequences on the PCB curvature near large electronic devices having high stiffness.

Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

2011 ◽  
Vol 423 ◽  
pp. 26-30
Author(s):  
S. Assif ◽  
M. Agouzoul ◽  
A. El Hami ◽  
O. Bendaou ◽  
Y. Gbati
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Dynamic Responses ◽  
Circuit Board ◽  
Joint Stress ◽  
Printed Circuit ◽  
Increasing Demand ◽  
Improved Model ◽  
Board Level

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

The Benefits of Flux-Coated Solder Preforms in a QFN Assembly Process

2015 ◽  
Vol 2015 (1) ◽  
pp. 000827-000832
Author(s):  
Brandon Judd ◽  
Maria Durham
Keyword(s):  
Mechanical Properties ◽  
Form Factor ◽  
Solder Joint ◽  
Circuit Board ◽  
Electrical Performance ◽  
Solder Paste ◽  
Assembly Process ◽  
Circuit Board Assembly ◽  
Difficult Challenge ◽  
Small Form Factor

The use of bottom terminated components (BTCs) such as quad-flat no-leads (QFNs) has become commonplace in the circuit board assembly world. This package offers several benefits including its small form factor, its excellent thermal and electrical performance, easy PCB trace routing, and reduced lead inductance. These components are generally attached to PWBs PCBs via solder paste. The design of these components with the large thermal pad, along with the tendency of solder paste to outgas during reflow from the volatiles in the flux, creates a difficult challenge in terms of voiding control within the solder joint. Voiding can have a serious effect on the performance of these components, including the mechanical properties of the joint as well as spot overheating. Solder preforms with a flux coating can be added to the solder paste to help reduce voiding. This study will focus on the benefits of utilizing solder preforms with modern flux coatings in conjunction with solder paste to help reduce voiding under QFNs, as well as the design and process parameters which provide optimal results.

Investigation on the failure criterion of reliability testing for Pb-free BGA packages

2010 ◽  
Vol 2010 (1) ◽  
pp. 000105-000109
Author(s):  
Weidong Xie ◽  
Tae-Kyu Lee ◽  
Kuo-Chuan Liu ◽  
Jie Xue
Keyword(s):  
Solder Joint ◽  
Failure Criterion ◽  
Reliability Testing ◽  
Threshold Values ◽  
Joint Failure ◽  
Failure Distribution ◽  
Free Solder ◽  
The Impact ◽  
Different Sources ◽  
Over Time

Daisy-chained test vehicles are commonly used in board level reliability testing. By continuously monitoring the in-situ daisy chain resistance change over time, a failure could be captured during cycling and eventually the failure data could be used to establish the solder joints failure distribution under different testing conditions. One of the most debatable matters is that when should one to determine a failure to occur. Per IPC 9701A [1] a failure is defined as 10 1000-ohm events in 1 micro-second duration for event detector or 20% increase over the baseline resistance for data logger. Other threshold values such as 100, 300, or 500 ohms are also commonly used by packaging reliability community. Such a wide range of failure threshold values may introduce significant delta in terms of cycle numbers for Pb-free solder joints if different criteria would be used as reported by Henshall, etc [2]. Therefore a systematic study of the impact of using such diversified resistance values on the final failure distribution is necessary and important such that no big difference among reliability results from different sources. The purpose of this study is to investigate the impact of different failure thresholds on Pb-free solder joint failure distribution for most commonly used packages. The test vehicle, designed on an 8″×15″ double-sided printed circuit board (PCB) with multiple test sites, was populated on both sides with daisy-chained components. To reflect the real situation, the components were selected to include different package types (FCBGA, PBGA, CSP, QFN, etc), different pitches (0.4–1.0 mm), and different package size (6–50mm). The assembled test vehicles then went through 0C–100C thermal cycling, the cycle numbers corresponding to different resistance thresholds were recorded and compared. The test results showed that the failure threshold has significant impact on Pb-free solder joint failure distribution, thus it is important to unify the failure criterion such that the reliability results from different sources could be compared side by side. For some packages especially small wire-bond packages that have relatively low baseline resistance, the 20% failure criterion may be too sensitive to the resistivity changes caused not by solder joint failure but other events such as connection cable resistivity change over time or temperature.

Failure Analysis of Halogen-Free Printed Circuit Board Assembly Under Board-Level Drop Test

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
Hung-Jen Chang ◽  
Chau-Jie Zhan ◽  
Tao-Chih Chang ◽  
Jung-Hua Chou
Keyword(s):  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Printed Circuit Board Assembly ◽  
Printed Circuit ◽  
Plastic Ball ◽  
Circuit Board Assembly ◽  
Halogen Free ◽  
Board Level ◽  
The Impact

In this study, a lead-free dummy plastic ball grid array component with daisy-chains and Sn4.0Ag0.5Cu Pb-free solder balls was assembled on an halogen-free high density interconnection printed circuit board (PCB) by using Sn1.0Ag0.5Cu solder paste on the Cu pad surfaces of either organic solderable preservative (OSP) or electroless nickel immersion gold (ENIG). The assembly was tested for the effect of the formation extent of Ag3Sn intermetallic compound. Afterward a board-level pulse-controlled drop test was conducted on the as-reflowed assemblies according to the JESD22-B110 and JESD22-B111 standards, the impact performance of various surface finished halogen-free printed circuit board assembly was evaluated. The test results showed that most of the fractures occurred around the pad on the test board first. Then cracks propagated across the outer build-up layer. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. Interfacial stresses numerically obtained by the transient stress responses supported the test observation as the simulated initial crack position was the same as that observed.

SAC–xTiO2 nano-reinforced lead-free solder joint characterizations in ultra-fine package assembly

2018 ◽  
Vol 30 (1) ◽  
pp. 1-13 ◽  
Author(s):  
Fakhrozi Che Ani ◽  
Azman Jalar ◽  
Abdullah Aziz Saad ◽  
Chu Yee Khor ◽  
Roslina Ismail ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Solder Joint ◽  
Solder Joints ◽  
Ion Beam ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Content Type ◽  
X Ray ◽  
Free Solder

Purpose This paper aims to investigate the characteristics of ultra-fine lead-free solder joints reinforced with TiO2 nanoparticles in an electronic assembly. Design/methodology/approach This study focused on the microstructure and quality of solder joints. Various percentages of TiO2 nanoparticles were mixed with a lead-free Sn-3.5Ag-0.7Cu solder paste. This new form of nano-reinforced lead-free solder paste was used to assemble a miniature package consisting of an ultra-fine capacitor on a printed circuit board by means of a reflow soldering process. The microstructure and the fillet height were investigated using a focused ion beam, a high-resolution transmission electron microscope system equipped with an energy dispersive X-ray spectrometer (EDS), and a field emission scanning electron microscope coupled with an EDS and X-ray diffraction machine. Findings The experimental results revealed that the intermetallic compound with the lowest thickness was produced by the nano-reinforced solder with a TiO2 content of 0.05 Wt.%. Increasing the TiO2 content to 0.15 Wt.% led to an improvement in the fillet height. The characteristics of the solder joint fulfilled the reliability requirements of the IPC standards. Practical implications This study provides engineers with a profound understanding of the characteristics of ultra-fine nano-reinforced solder joint packages in the microelectronics industry. Originality/value The findings are expected to provide proper guidelines and references with regard to the manufacture of miniaturized electronic packages. This study also explored the effects of TiO2 on the microstructure and the fillet height of ultra-fine capacitors.

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