Modelling the Performance of Lead-Free Solder Interconnects for Copper Bumped Flip-Chip Devices

2003 ◽  
Author(s):  
Hua Lu ◽  
Chris Bailey
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Conductive Adhesives ◽  
Solder Interconnects ◽  
Flip Chips ◽  
Solder Bumps ◽  
Solder Volume ◽  
Joint Properties ◽  
Free Solder

Traditionally, before flip chips can be assembled the dies have to be attached with solder bumps. This process involves the deposition of metal layers on the Al pads on the dies and this is called the under bump metallurgy (UBM). In an alternative process, however, Copper (Cu) columns can be used to replace solder bumps and the UBM process may be omitted altogether. After the bumping process, the bumped dies can be assembled on to the printed circuit board (PCB) by using either solder or conductive adhesives. In this work, the reliability issues of flip chips with Cu column bumped dies have been studied. The flip chip lifetime associated with the solder fatigue failure has been modeled for a range of geometric parameters. The relative importance of these parameters is given and solder volume has been identified as the most important design parameter for long-term reliability. Another important problem that has been studied in this work is the dissolution of protection metals on the pad and Cu column in the reflow process. For small solder joints the amount of Cu which dissolves into the molten solder after the protection layers have worn out may significantly affect solder joint properties.

Shock and Vibration of Solder Bumped Flip Chip on Organic Coated Copper Boards

1996 ◽  
Vol 118 (2) ◽  
pp. 101-104 ◽  
Author(s):  
John Lau ◽  
Eric Schneider ◽  
Tom Baker
Keyword(s):  
Mathematical Analysis ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Plane Shock ◽  
Printed Circuit ◽  
Flip Chips ◽  
Solder Bumps ◽  
Out Of Plane ◽  
Vibration Tests

The reliability of solder bumped flip chips on organic coated copper (OCC) printed circuit board (PCB) has been studied by shock and vibration tests and a mathematical analysis. Two different chip sizes (7 mm and 14 mm on a side) have been studied, and the larger chips have many internal solder bumps. For the in-plane and out-of-plane and out-of-plane shock tests, the chips were assembled with and without underfill encapsulants. However, for the out-of-plane vibration tests all the chips were underfilled with epoxy.

Evaluation of a Conductive Adhesive Based Approach to Lead Free Flip Chip Assembly

2002 ◽  
Author(s):  
Muthiah Venkateswaran ◽  
Peter Borgesen ◽  
K. Srihari
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Critical Evaluation ◽  
Conductive Adhesive ◽  
Circuit Board ◽  
Lead Free ◽  
Conductive Adhesives ◽  
Flip Chip Assembly ◽  
Placement Machine

Electrically conductive adhesives are emerging as a lead free, flux less, low temperature alternative to soldering in a variety of electronics and optoelectronics applications. Some of the potential benefits are obvious, but so far the adhesives have some limitations as well. The present work offers a critical evaluation of one approach to flip chip assembly, which lends itself particularly well to use with a high speed placement machine. Wafers were bumped by stencil printing of a thermoset conductive adhesive, which was then fully cured. In assembly, the conductive adhesive paste was stencil printed onto the pads of a printed circuit board and cured after die placement. The printing process was optimized to ensure robust assembly and the resulting reliability assessed.

Failure Analysis Techniques for Lead-Free Solder Joints

2005 ◽  
Author(s):  
Todd Castello ◽  
Dan Rooney ◽  
Dongkai Shangguan
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Board ◽  
Failure Modes ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Printed Circuit Board Assembly ◽  
Analysis Techniques ◽  
Solder Interconnects ◽  
Free Solder

Abstract Printed circuit board assembly with lead free solder is now a reality for most global electronics manufacturers. Extensive research and development has been conducted to bring lead free assembly processes to a demonstrated proficiency. Failure analysis has been an integral part of this effort and will continue to be needed to solve problems in volume production. Many failure analysis techniques can be directly applied to study lead free solder interconnects, while others may require some modification in order to provide adequate analysis results. In this paper, several of the most commonly applied techniques for solder joint failure analysis will be reviewed, including visual inspection, x-ray radiography, mechanical strength testing, dye & pry, metallography, and microscopy/photomicrography, comparing their application to lead bearing and lead free solder interconnects. Common failure modes and mechanisms will be described with examples specific to lead free solders, following PCB assembly as well as after accelerated reliability tests.

Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW)

2011 ◽  
Vol 2011 (1) ◽  
pp. 000446-000454
Author(s):  
J. H. Lau ◽  
C-J Zhan ◽  
P-J Tzeng ◽  
C-K Lee ◽  
M-J Dai ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Organic Substrate ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
3D Ic ◽  
Solder Bumps ◽  
Bottom Side ◽  
Free Solder ◽  
Key Enabling Technologies

The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with RDL (redistribution layer) on both sides, IPD (integrated passive devices) and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and then overmolded on its top side for pick and place purposes. The interposer’s bottom-side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly and reliability are highlighted.

Analysis of the Micro-Mechanical Properties in Aged Lead-Free, Fine Pitch Flip Chip Joints

2003 ◽  
Author(s):  
Changqing Liu ◽  
Paul Conway ◽  
Dezhi Li ◽  
Michael Hendriksen
Keyword(s):  
Shear Strength ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Initial Period ◽  
Electroless Nickel ◽  
Circuit Board ◽  
Solder Paste ◽  
Soldering Process ◽  
Joint Reliability ◽  
Solder Bumps

This research seeks to characterize the micro-mechanical behavior of Sn-Ag-Cu solder bumps/joints generated by fine feature flip chip fabrication and assembly processes. The bumps used for characterization were produced by stencil deposition of solder paste onto an electroless Nickel UBM, followed by a bump-forming reflow soldering process and the final assembly joints were then achieved by a subsequent reflow of die onto a fine feature Printed Circuit Board (PCB). The bumps and joints were aged at either 80°C or 150°C for up to 1.5 months and then analyzed by means of micro-shear testing and nano-indentation techniques. The shear test of the aged bumps showed a slight increase in shear strength after an initial period of aging (∼ 50h) as compared to as-manufactured bumps, but a decrease after longer aging (e.g. 440 h). A brittle Ag3Sn phase formed as large lamellae in the solder and along the interface between the Cu on the PCB during the initial aging, and is attributed to the increase of shear strength, along with the refinement of the bump microstructure. However, as the time of aging extended, the solder bumps were softened due to grain growth and re-crystallization. It was found that the formation of brittle phases in the solder and along the interfaces caused localized stress concentration, which can significantly affect joint reliability. In addition, Nano-testing identified a lamellar Au-rich structure, formed in the solder and interface of the solder/PCB in the joints after the aging process. These are believed to be detrimental to joint reliability.

Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 mm Multi-Project Wafer (MPW)

2011 ◽  
Vol 8 (4) ◽  
pp. 171-178 ◽  
Author(s):  
J. H. Lau ◽  
C.-J. Zhan ◽  
P.-J. Tzeng ◽  
C.-K. Lee ◽  
M.-J. Dai ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Organic Substrate ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
3D Ic ◽  
Solder Bumps ◽  
Bottom Side ◽  
Free Solder ◽  
Key Enabling Technologies

The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with an RDL (redistribution layer) on both sides, IPD (integrated passive devices), and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and is then overmolded on its top side for pick and place purposes. The interposer's bottom side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly, and reliability are highlighted.

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

Sign in / Sign up

Export Citation Format

Share Document