Evaluation of a Conductive Adhesive Based Approach to Lead Free Flip Chip Assembly

2002 ◽  
Author(s):  
Muthiah Venkateswaran ◽  
Peter Borgesen ◽  
K. Srihari
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Critical Evaluation ◽  
Conductive Adhesive ◽  
Circuit Board ◽  
Lead Free ◽  
Conductive Adhesives ◽  
Flip Chip Assembly ◽  
Placement Machine

Electrically conductive adhesives are emerging as a lead free, flux less, low temperature alternative to soldering in a variety of electronics and optoelectronics applications. Some of the potential benefits are obvious, but so far the adhesives have some limitations as well. The present work offers a critical evaluation of one approach to flip chip assembly, which lends itself particularly well to use with a high speed placement machine. Wafers were bumped by stencil printing of a thermoset conductive adhesive, which was then fully cured. In assembly, the conductive adhesive paste was stencil printed onto the pads of a printed circuit board and cured after die placement. The printing process was optimized to ensure robust assembly and the resulting reliability assessed.

Modelling the Performance of Lead-Free Solder Interconnects for Copper Bumped Flip-Chip Devices

2003 ◽  
Author(s):  
Hua Lu ◽  
Chris Bailey
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Conductive Adhesives ◽  
Solder Interconnects ◽  
Flip Chips ◽  
Solder Bumps ◽  
Solder Volume ◽  
Joint Properties ◽  
Free Solder

Traditionally, before flip chips can be assembled the dies have to be attached with solder bumps. This process involves the deposition of metal layers on the Al pads on the dies and this is called the under bump metallurgy (UBM). In an alternative process, however, Copper (Cu) columns can be used to replace solder bumps and the UBM process may be omitted altogether. After the bumping process, the bumped dies can be assembled on to the printed circuit board (PCB) by using either solder or conductive adhesives. In this work, the reliability issues of flip chips with Cu column bumped dies have been studied. The flip chip lifetime associated with the solder fatigue failure has been modeled for a range of geometric parameters. The relative importance of these parameters is given and solder volume has been identified as the most important design parameter for long-term reliability. Another important problem that has been studied in this work is the dissolution of protection metals on the pad and Cu column in the reflow process. For small solder joints the amount of Cu which dissolves into the molten solder after the protection layers have worn out may significantly affect solder joint properties.

Effects of Corner/Edge Bonding and Underfill Properties on the Thermal Cycling Performance of Lead Free Ball Grid Array Assemblies

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
P. Borgesen ◽  
D. Blass ◽  
M. Meilunas
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Ball Grid Array ◽  
Cycling Performance ◽  
Circuit Board ◽  
Lead Free ◽  
Sac305 Solder ◽  
Solder Balls ◽  
Selection Of

Underfilling will almost certainly improve the performance of an area array assembly in drop, vibration, etc. However, depending on the selection of materials, the thermal fatigue life may easily end up worse than without an underfill. This is even more true for lead free than for eutectic SnPb soldered assemblies. If reworkability is required, the bonding of the corners or a larger part of the component edges to the printed circuit board (PCB), without making contact with the solder joints, may offer a more attractive materials selection. A 30 mm flip chip ball grid array (FCBGA) component with SAC305 solder balls was attached to a PCB and tested in thermal cycling with underfills and corner/edge bonding reinforcements. Two corner bond materials and six reworkable and nonreworkable underfills with a variety of mechanical properties were considered. All of the present underfills reduced the thermal cycling performance, while edge bonding improved it by up to 50%. One set of the FCBGAs was assembled with a SnPb paste and underfilled with a soft reworkable underfill. Surprisingly, this improved the thermal cycling performance slightly beyond that of the nonunderfilled assemblies, providing up to three times better life than for those assembled with a SAC305 paste.

Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint

2004 ◽  
Author(s):  
Norman J. Armendariz ◽  
Prawin Paulraj
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Gold Surface ◽  
Circuit Board ◽  
Lead Free ◽  
Processing Temperature ◽  
The European Union ◽  
Printed Circuit ◽  
Higher Temperature ◽  
Tin Silver Copper

Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications

2002 ◽  
Vol 124 (3) ◽  
pp. 205-211 ◽  
Author(s):  
John H. Lau ◽  
S. W. Ricky Lee ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Cross Sections ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Circuit Board ◽  
Test Results ◽  
Pcb Assembly ◽  
Creep Analysis ◽  
Chip Scale Package ◽  
Time Dependent Analysis

An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the thermal cycling test results of the micro VIP CSP PCB assembly is presented.

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