Analysis of the Micro-Mechanical Properties in Aged Lead-Free, Fine Pitch Flip Chip Joints

2003 ◽  
Author(s):  
Changqing Liu ◽  
Paul Conway ◽  
Dezhi Li ◽  
Michael Hendriksen
Keyword(s):  
Shear Strength ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Initial Period ◽  
Electroless Nickel ◽  
Circuit Board ◽  
Solder Paste ◽  
Soldering Process ◽  
Joint Reliability ◽  
Solder Bumps

This research seeks to characterize the micro-mechanical behavior of Sn-Ag-Cu solder bumps/joints generated by fine feature flip chip fabrication and assembly processes. The bumps used for characterization were produced by stencil deposition of solder paste onto an electroless Nickel UBM, followed by a bump-forming reflow soldering process and the final assembly joints were then achieved by a subsequent reflow of die onto a fine feature Printed Circuit Board (PCB). The bumps and joints were aged at either 80°C or 150°C for up to 1.5 months and then analyzed by means of micro-shear testing and nano-indentation techniques. The shear test of the aged bumps showed a slight increase in shear strength after an initial period of aging (∼ 50h) as compared to as-manufactured bumps, but a decrease after longer aging (e.g. 440 h). A brittle Ag3Sn phase formed as large lamellae in the solder and along the interface between the Cu on the PCB during the initial aging, and is attributed to the increase of shear strength, along with the refinement of the bump microstructure. However, as the time of aging extended, the solder bumps were softened due to grain growth and re-crystallization. It was found that the formation of brittle phases in the solder and along the interfaces caused localized stress concentration, which can significantly affect joint reliability. In addition, Nano-testing identified a lamellar Au-rich structure, formed in the solder and interface of the solder/PCB in the joints after the aging process. These are believed to be detrimental to joint reliability.

Analysis of the Micro-Mechanical Properties in Aged Lead-Free, Fine Pitch Flip Chip Joints

2004 ◽  
Vol 126 (3) ◽  
pp. 359-366 ◽  
Author(s):  
Changqing Liu ◽  
Paul Conway ◽  
Dezhi Li ◽  
Michael Hendriksen
Keyword(s):  
Shear Strength ◽  
Aging Process ◽  
Flip Chip ◽  
Initial Period ◽  
Bulk Solder ◽  
The Body ◽  
Nano Indentation ◽  
Joint Reliability ◽  
Fine Pitch ◽  
Solder Bumps

This research seeks to characterize the micro-mechanical behavior of Sn-Ag-Cu solder bumps/joints generated by fine pitch flip chip assembly processes. The solder bumps and joints that were aged at either 80 °C or 150 °C for up to 440 hours (∼18 days); have been studied by an analysis using micro-shear testing and nano-indentation techniques. The shear test of the aged bumps showed a slight increase in shear strength after an initial period of aging (∼50 hours) as compared to the non-aged bumps, but a decrease after longer aging (e.g. 440 hours). A brittle Ag3Sn phase formed as large stick-like features in the body of bulk solder and near the interface of solder/UBM during the initial aging, and is attributed with the increase of shear strength, along with the refinement of the bump microstructure. However, as the time of aging extended, the solder bumps were softened due to grain growth and re-crystallization. It was found that the formation of brittle phases in the body of solder and along the interfaces caused localized stress concentration, which can significantly affect joint reliability. In addition, Nano-testing identified a large lamellar Au-rich structure, formed in the solder and interface of the solder/PCB in the joints after the aging process at 150 °C. These are believed to be detrimental to joint reliability.

The Effect of Solder Paste Volume and Reflow Ambient Atmosphere on Reliability of CBGA Assemblies

1999 ◽  
Vol 123 (3) ◽  
pp. 284-289 ◽  
Author(s):  
Y. P. Wu ◽  
P. L. Tu ◽  
Yan C. Chan
Keyword(s):  
Fatigue Life ◽  
Printed Circuit Board ◽  
Theoretical Models ◽  
Circuit Board ◽  
Ambient Atmosphere ◽  
Solder Paste ◽  
Remarkable Effect ◽  
Soldering Process ◽  
Vibration Fatigue ◽  
And Performance

To investigate the effect of stencil thickness and reflow ambient atmosphere on the reliability of ceramic ball grid array (CBGA) assemblies, three levels of stencil thickness, 0.10, 0.15, and 0.20 mm, were used to print solder paste on printed circuit board (PCB). After the CBGA modules were placed on PCBs, the specimens were divided into two groups, and reflowed in nitrogen and compressed air separately. Properties of the six groups of assemblies, such as shear strength, bending fatigue life, thermal shock cycles, and vibration fatigue life, were tested to find out the optimum assembling process. The results show that assemblies prepared with a stencil 0.15 mm thick yield maximized performance. And the nitrogen ambient atmosphere demonstrates a remarkable effect on improving the fatigue life. Theoretical models are given to qualitatively explain the relationship between the solder joint volume and performance. This work provides a guideline on how to determine the soldering process parameters of CBGA assemblies.

Modelling the Performance of Lead-Free Solder Interconnects for Copper Bumped Flip-Chip Devices

2003 ◽  
Author(s):  
Hua Lu ◽  
Chris Bailey
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Conductive Adhesives ◽  
Solder Interconnects ◽  
Flip Chips ◽  
Solder Bumps ◽  
Solder Volume ◽  
Joint Properties ◽  
Free Solder

Traditionally, before flip chips can be assembled the dies have to be attached with solder bumps. This process involves the deposition of metal layers on the Al pads on the dies and this is called the under bump metallurgy (UBM). In an alternative process, however, Copper (Cu) columns can be used to replace solder bumps and the UBM process may be omitted altogether. After the bumping process, the bumped dies can be assembled on to the printed circuit board (PCB) by using either solder or conductive adhesives. In this work, the reliability issues of flip chips with Cu column bumped dies have been studied. The flip chip lifetime associated with the solder fatigue failure has been modeled for a range of geometric parameters. The relative importance of these parameters is given and solder volume has been identified as the most important design parameter for long-term reliability. Another important problem that has been studied in this work is the dissolution of protection metals on the pad and Cu column in the reflow process. For small solder joints the amount of Cu which dissolves into the molten solder after the protection layers have worn out may significantly affect solder joint properties.

Shock and Vibration of Solder Bumped Flip Chip on Organic Coated Copper Boards

1996 ◽  
Vol 118 (2) ◽  
pp. 101-104 ◽  
Author(s):  
John Lau ◽  
Eric Schneider ◽  
Tom Baker
Keyword(s):  
Mathematical Analysis ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Plane Shock ◽  
Printed Circuit ◽  
Flip Chips ◽  
Solder Bumps ◽  
Out Of Plane ◽  
Vibration Tests

The reliability of solder bumped flip chips on organic coated copper (OCC) printed circuit board (PCB) has been studied by shock and vibration tests and a mathematical analysis. Two different chip sizes (7 mm and 14 mm on a side) have been studied, and the larger chips have many internal solder bumps. For the in-plane and out-of-plane and out-of-plane shock tests, the chips were assembled with and without underfill encapsulants. However, for the out-of-plane vibration tests all the chips were underfilled with epoxy.

Rapid Prototyping Tape Stencils for the Application of Solder Paste

2017 ◽  
Vol 2017 (1) ◽  
pp. 000652-000658
Author(s):  
Mimi X. Yang ◽  
Karen Dowling ◽  
Debbie Senesky ◽  
H.-S. Philip Wong
Keyword(s):  
Rapid Prototyping ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Solder Paste ◽  
Electrically Conductive ◽  
Printed Circuit ◽  
Solder Bumps ◽  
Small Device ◽  
Bond Pads ◽  
Silicon Device

Abstract This works describes a promising method for rapid prototyping tape stencils for the application of solder paste. This process is appropriate for research settings requiring developmental flexibility and the ability to deal with small device dies. This work compares the volume of solder paste deposited versus aperture volume for several common tape materials and several common printed circuit board (PCB) stencil materials. The solder deposits are then reflowed to identify which aperture and solder paste parameters can generate successful solder bumps. Electrically conductive solder bonds for small bond pads (100 μm and larger) are demonstrated between silicon device dies and glass dies using this process.

CONTROLLING AND OPTIMIZATION OF THERMAL PROFILE IN REFLOW SOLDERING

2009 ◽  
Vol 23 (06n07) ◽  
pp. 1949-1955
Author(s):  
JIANWEI SHI ◽  
PENG HE ◽  
XIAOCHUN LV
Keyword(s):  
Solder Joint ◽  
Circuit Board ◽  
Solder Paste ◽  
Thermal Profile ◽  
Reflow Soldering ◽  
Soldering Process ◽  
Joint Reliability ◽  
Controlling Parameter ◽  
Technical Evaluation ◽  
Reliability Of Solder Joints

Heating factor, Q is a quantitative parameter describing a process of reflow soldering. It can be used to evaluate a reflow soldering process and the reliability of solder joints. The value of Q is directly related to the energy absorbed by solder joint during heating and the morphology of Intermetallic Compound formed at the interface between solder and pad. Electronic product manufacturers use heating factor as a technical evaluation parameter to guide the adjustment of reflow soldering process and the optimization of reflow soldering curve, to ensure the best reliability of the circuit board. Solder paste manufacturers use heating factor to represent characteristics of their reflow soldering products, and to customize products according to consumer's requests. Equipment manufacturers for reflow soldering use heating factor as an important controlling parameter to establish automatic system for managing solder joint reliability. A reliable soldering result can be achieved using the automatic reflow management system, to control and optimize thermal profile, which leads to the adjustment of the heating factor.

Fracture Mechanics Analysis of Low Cost Solder Bumped Flip Chip Assemblies With Imperfect Underfills

2000 ◽  
Vol 122 (4) ◽  
pp. 306-310 ◽  
Author(s):  
John H. Lau ◽  
S.-W. Ricky Lee
Keyword(s):  
Fracture Mechanics ◽  
Solder Joint ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Strain Energy Release ◽  
Circuit Board ◽  
Temperature Dependent ◽  
Joint Reliability

Solder joint reliability of flip chip on various thickness of printed circuit board with imperfect underfill is presented in this study. Emphasis is placed on the determination of the temperature-dependent stress and plastic strain at the corner solder joint with different crack (delamination) lengths. Also, the strain energy release rate and phase angle at the crack tip of the interface between the underfill and solder mask are obtained by fracture mechanics. [S1043-7398(00)01104-X]

Electrolytic Deposition of Fine Pitch Sn/Cu Solder Bumps for Flip Chip Packaging

2012 ◽  
Vol 2012 (1) ◽  
pp. 000729-000734
Author(s):  
Stephen Kenny ◽  
Kai Matejat ◽  
Sven Lamprecht ◽  
Olivier Mann
Keyword(s):  
Copper Alloy ◽  
Flip Chip ◽  
Solder Bump ◽  
Electroless Nickel ◽  
Practical Experience ◽  
Electrolytic Deposition ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Solder Bumps

Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate alloy solder paste. The continuing trend towards increased miniaturization and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 150μm for these applications. This paper describes latest developments in the electrolytic deposition of solder to replace the stencil printing process; results from production of 90μm bump pitch solder arrays with tin/copper alloy are given. The solder bump is produced with a specially developed electrolytic tin process which fills a photo resist defined structure on the SRO. The photoresist dimensions determine the volume of solder produced and the subsequent bump height after reflow. Investigations on the bump reliability after reflow are shown including copper alloy concentration at 0.7% and x-ray investigation to confirm uniform metal deposition. The self centering mechanism found in the bump production process during reflow is presented and the capability to correct photoresist registration issues. The solder bumps are shown as deposited onto an electroless nickel/gold or electroless nickel/palladium/gold final finish which serves also as a barrier layer to copper diffusion into the solder bump. Discussion of further development work in the production of alloys of tin/copper together with silver are given with first test results.

Rheology Characterization of Solder Paste

2017 ◽  
Author(s):  
Flávia V. Barbosa ◽  
Pedro E. A. Ribeiro ◽  
Maria F. Cerqueira ◽  
Delfim F. Soares ◽  
José C. F. Teixeira ◽  
...  
Keyword(s):  
Shear Rate ◽  
Production Efficiency ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Creep Recovery ◽  
Solder Paste ◽  
Electronic Components ◽  
Increase Production Efficiency ◽  
Reflow Soldering ◽  
Soldering Process

Reflow soldering process is widely implemented in the electronics industry. This method allows the attachment of electronic components to a printed circuit board (PCB) through the melting of solder paste, which makes the interconnection between them. The reflow soldering process must ensures the correctly melting of the solder paste and heating of the adjoining surfaces, without the electronic components suffer overheating or any other type of damage. Solder paste is the most widespread material in the SMT (Surface Mount Technology) process using reflow soldering. An ideal solder paste will increase production efficiency, decreasing the amount of defects associated with the reflow soldering process. However, several factors affects the performance of the solder paste, from rheology, printability, and reliability to the adhesion strength of components and the ability to avoid defects related to reflow. Therefore, all these factors need to be considered during the selection of a solder paste for a specific application. The rheological properties were determined using both a double cylinder (PHYSICA-RHEOLAB MC1) and a double plate (Malvern) rheometers. The later enable the determination of viscoelastic properties. The present paper analyses the rheological behavior of a SAC405 solder paste, a mixture containing a metal alloy powder (25–45 μm) and a flux which at its base is a resin. The tests were carried out at conditions (temperature and shear rate) of relevance to the printing process. The results obtained show that the paste viscosity closely follows the Herschel-Bulkley model and shows a thixotropic behavior without fully recovery between applications. In addition, the viscosity decreases with the increase of shear rate confirming that the solder paste is a non-Newtonian fluid, shear thinning in behavior. The oscillatory tests have shown that the transition from elastic to viscous behavior occurs at a shear stress above 35 Pa. On the other hand, the creep/recovery test confirms that the level of solicitation influences the capacity of recovery of the solder paste.

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

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