Wafer Level Micropackaging of MEMS Devices Using Thin Film Anodic Bonding

2002 ◽  
Vol 729 ◽  
Author(s):  
Lauren E. S. Rohwer ◽  
Andrew D. Oliver ◽  
Melissa V. Collins
Keyword(s):  
Shear Strength ◽  
Test Sample ◽  
Anodic Bonding ◽  
Mems Devices ◽  
Wafer Level ◽  
Thermal Actuators ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Leak Testing ◽  
Before And After

AbstractA wafer level packaging technique that involves anodic bonding of Pyrex wafers to released surface micromachined wafers is demonstrated. Besides providing a hermetic seal, this technique allows full wafer release, provides protection during die separation, and offers the possibility of integration with optoelectronic devices. Anodic bonding was performed under applied voltages up to 1000 V, and temperatures ranging from 280 to 400°C under vacuum (10-4Torr). The quality of the bonded interfaces was evaluated using shear strength testing and leak testing. The shear strength of Pyrex-to-polysilicon and aluminum bonds was ∼10-15 MPa. The functionality of surface micromachined polysilicon devices was tested before and after anodic bonding. 100% of thermal actuators, 94% of torsional ratcheting actuators, and 70% of microengines functioned after bonding. The 70% yield was calculated from a test sample of 25 devices.

On Hermeticity Detection of Wafer Level Packages for MEMS Devices

2005 ◽  
Author(s):  
A. Goswami ◽  
B. Han ◽  
C. Wade ◽  
A. Chien
Keyword(s):  
Mems Devices ◽  
Rate Measurement ◽  
Wafer Level ◽  
Measurement Sensitivity ◽  
Leak Test ◽  
Design Assessment ◽  
Hermetic Packaging ◽  
Wafer Level Packaging ◽  
Test Parameters ◽  
Leak Testing

Wafer level packaging has emerged as one of the promising solutions for hermetic packaging of MEMS devices. Detection of the level of hermeticity of the package is essential for reliability and design assessment of the devices. Traditionally, hermeticity has been tested using Helium based fine leak testing. However, there are limitations when this technique is used for the hermeticity detection of small volumes (< 10−3 cc) that are typical in wafer level packages. This paper reviews the helium fine leak test, its limitations and the influence of the different test parameters on leakage rate measurement are analyzed for wafer level packages with small cavity volumes. The results indicate a need for development of a new hermeticity measurement technique to achieve the measurement sensitivity required for wafer level packages.

Wafer Level Package for MEMS with TSVs and Hermetic Seal

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002314-002335
Author(s):  
Akinori Shiraishi ◽  
Mitsutoshi Higashi ◽  
Kei Murayama ◽  
Yuichi Taguchi ◽  
Kenichi Mori
Keyword(s):  
Silicon Wafer ◽  
Adhesive Bonding ◽  
Anodic Bonding ◽  
Back Side ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Mems Device ◽  
Bonding Method ◽  
Wafer Level Package

In recent years, downsizing of MEMS package and high accuracy MEMS device mounting have been strongly required from expanding applications that using MEMS not only for industrial and automobile but also for consumer typified mobile phone. In order to achieve that, it is appropriate to use Silicon package that can be mounted at wafer level packaging. Silicon package is made of monocrystal silicon wafer. The deep cavity is fabricated on monocrystal silicon wafer by Wet or Dry etching. And MEMS device can be mounted on the cavity. The electrical connecting between front side and back side of cavity portion is achieved by TSVs that located on the bottom of cavity. Hermetic seal can be achieved by using glass or silicon wafer bonding method. By using a driver device wafer (before dicing) as the cap for hermetic seal, smaller size and smaller number of parts module can be fabricated. In this report, methods and designs for hermetic seal with wafer level process were examined. Methods that applied were polyimide adhesive bonding, anodic bonding and Au-In solder bonding. Location of TSVs on the bottom of cavity and thickness of diaphragm with TSVs was also examined. Silicon package for piezo type gyro MEMS that designed by the result of evaluation was fabricated. This package used optimized Au-In solder bonding for hermetic seal and optimized location of TSVs for interconnection. That was designed over 50% thinner than conventional ceramic packages. Characteristics of hermetic seal were evaluated by Q factor of gyro MEMS that mounted inside of the silicon package. It is confirmed that performance of sealing are good enough for running of the MEMS.

Wafer Bonding Processes for the Manufacture of Microsystems

2008 ◽  
Author(s):  
Tony Rogers ◽  
Nick Aitken
Keyword(s):  
Bond Strength ◽  
Wafer Bonding ◽  
High Efficiency ◽  
Glass Frit ◽  
Acoustic Microscopy ◽  
Anodic Bonding ◽  
High Yield ◽  
Mems Devices ◽  
Wafer Level ◽  
Wafer Level Packaging

Wafer bonding is a widely used step in the manufacture of Microsystems, and serves several purposes: • Structural component of the MEMS device. • First level packaging. • Encapsulation of vacuum or controlled gas. In addition the technology is becoming more widely used in IC fabrication for wafer level packaging (WLP) and 3D integration. It is also widely used for the fabrication of micro fluidic structures and in the manufacture of high efficiency LED’s. Depending on the application, temperature constraints, material compatibility etc. different wafer bonding processes are available, each with their own benefits and drawbacks. This paper describes various wafer bonding processes that are applicable, not only to silicon, but other materials such as glass and quartz that are commonly used in MEMS devices. The process of selecting the most appropriate bonding process for the particular application is presented along with examples of anodic, glass frit, eutectic, direct, adhesive and thermo-compression bonding. The examples include appropriate metrology for bond strength and quality. The paper also addresses the benefits of being able to treat the wafer surfaces in-situ prior to bonding in order to improve yield and bond strength, and also discusses equipment requirements for achieving high yield wafer bonding, along with high precision alignment accuracy, good force and temperature uniformity, high wafer throughput, etc. Some common problems that can affect yield are identified and discussed. These include local temperature variations, that can occur with anodic bonding, and how to eliminate them; how to cope with materials of different thermal expansion coefficient; how best to deal with out-gassing and achieve vacuum encapsulation; and procedures for multi-stacking wafers of differing thicknesses. The presentation includes infra-red and scanning acoustic microscopy images of various bond types, plus some examples of what can go wrong if the correct manufacturing protocol is not maintained.

Hermetic Packaging Technique Featuring Through-Wafer Interconnects and Low Temperature Direct Bond

2008 ◽  
Author(s):  
James Lee ◽  
Tony Rogers
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
High Strength ◽  
Mems Devices ◽  
Wafer Level ◽  
Direct Bond ◽  
Hermetic Packaging ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Silicon Silicon

A novel wafer level packaging method suitable for low production volumes, R&D, and multi-project wafers is presented, providing a hermetic seal suitable for vacuum encapsulation with wafers bonded at a low temperature. Hermetic through-wafer interconnects are bump bonded to a CMOS chip encapsulated by bonding a cap wafer after activating surfaces with free radicals, the Silicon-Silicon direct bond is then annealed to a high strength at 200°C to avoid chip damage. The application for which this system is proposed is an implantable multi-contact active nerve electrode for the treatment of epilepsy via vagus nerve stimulation. Although intended for human implantation of integrated systems, this technology may be applied across a range of devices requiring hermetic or vacuum sealing and through-wafer interconnection. Solid electroplated through-wafer interconnects (aspect ratio 5) enable hermetic interconnection of direct bonded packages with low connection impedance, offering benefits across a range of packaging applications. A key feature of this packaging method is it’s versatility, the proposed embodiment features chip to wafer bonding with an ASIC, but the package is equally suitable for MEMS devices and also for wafer to wafer bonding.

Effects of Packaging Induced Stress on MEMS Devices and Its Improvements

2006 ◽  
Vol 326-328 ◽  
pp. 529-532
Author(s):  
Sung Hoon Choa ◽  
Moon Chul Lee ◽  
Yong Chul Cho
Keyword(s):  
Silicon On Insulator ◽  
Anodic Bonding ◽  
Mems Devices ◽  
Wafer Level ◽  
Process Technology ◽  
Molding Compound ◽  
Mems Packaging ◽  
Induced Stress ◽  
Induced Structure ◽  
Glass Process

In MEMS, packaging induced stress or stress induced structure deformation becomes increasing concerns since it directly affects the performance of the device. The conventional MEMS SOI (silicon-on-insulator) gyroscope, packaged using the anodic bonding at the wafer level and EMC (epoxy molding compound) molding, has a deformation of MEMS structure caused by thermal expansion mismatch. Therefore we propose a packaged SiOG (Silicon On Glass) process technology and more robust spring design.

Anodic Bonding of Silicon-Pyrex and Silicon-Soda Lime Glass at Room Temperature

2014 ◽  
Vol 1082 ◽  
pp. 420-423
Author(s):  
Muhammad Hafiz Ab Aziz ◽  
Zaliman Sauli ◽  
Vithyacharan Retnasamy ◽  
Hussin Kamarudin ◽  
Wan Mokhdzani Wan Norhaimi ◽  
...  
Keyword(s):  
Bond Strength ◽  
Wafer Bonding ◽  
Room Temperature ◽  
Bonding Temperature ◽  
Soda Lime ◽  
Anodic Bonding ◽  
Soda Lime Glass ◽  
Cleaning Process ◽  
Mems Devices ◽  
Before And After

Silicon wafer bonding opens possibilities in creating MEMS devices and anodic bonding is found to be the most relevant wafer bonding technique process in constructing and packaging MEMS. This paper reports on the bond strength comparison between silicon and different glass based materials via anodic bonding. Two types of glass based surface used pyrex and soda lime glass. Bonding temperature is set at room temperature while a high direct current voltage of 15kV. Experiments were carried out using an in-house designed anodic bonder and the bond strength were measured using a bond strength tester. The anodic approach process was done in two sets which are before and after the cleaning process for each sample. Results show that all samples showed higher bond strength after the cleaning process. Silicon-soda lime glass have higher bonding strength of 1950 Pa compared to silicon-pyrex bonding which only gives 1850 Pa of bond strength.

Shorting out bonding method for multi-stack anodic bonding and its application in wafer-level packaging

2020 ◽  
Vol 34 (32) ◽  
pp. 2050369
Author(s):  
Yifang Liu ◽  
Tingting Dai ◽  
Peiqin Xie ◽  
Lingyun Wang ◽  
Zhan Zhan ◽  
...  
Keyword(s):  
Anodic Bonding ◽  
Wafer Level ◽  
Temperature Property ◽  
Mems Packaging ◽  
Long Term Stability ◽  
Wafer Level Packaging ◽  
Voltage Division ◽  
Rc Circuit ◽  
Bonding Method

Silicon/glass anodic bonding is widely investigated during MEMS packaging of multi-stack structures. The electrical behavior of anode bonding can be described as the charging and discharging process of RC circuit. Here, we conduct the equivalent RC circuit model analysis and experimental investigation, and demonstrate that voltage division and electricity leakage are the dilemma for the conventional multi-stack anodic bonding. By using feedthrough, the feasibility and convenience of “shorting out bonding” is presented, which is exampled through the wafer-level packaging of the MEMS gyroscope. Result from the sensor’s vacuum characterization reveals that shorting out bonding for multi-stack silicon/glass structures is an effective method for wafer-level packaging due to long-term stability and low temperature property.‘

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