Simplified Thermal Model of Silicon Thermoelectric Microcooler for On-Chip Hot Spot Remediation

2007 ◽  
Author(s):  
Peng Wang ◽  
Avram Bar-Cohen
Keyword(s):  
Thermal Management ◽  
Material Properties ◽  
Hot Spots ◽  
Hot Spot ◽  
Design Tool ◽  
The Novel ◽  
Thermo Electric ◽  
Design And Optimization ◽  
Conventional Cooling ◽  
On Chip

Thermal management of on-chip hot spots has become an increasing challenge in recent years because such localized high flux hot spots can not be effectively removed by conventional cooling techniques. The authors have recently explored the novel use of the silicon chip itself as a solid state thermoelectric micrcooler (μTEC) for hot spot thermal management. This paper describes the development and application of a thermo-electric design tool based on closed-form equations for the primary variables. This tool can be used to effectively reduce the complexity and required time for the design and optimization of the silicon microcooler geometry and material properties for on-chip hot spot remediation.

Thermoelectric Self-Cooling on Germanium Chip

2010 ◽  
Author(s):  
Peng Wang ◽  
Avram Bar-Cohen
Keyword(s):  
Thermal Management ◽  
Hot Spots ◽  
Hot Spot ◽  
Thermal Contact ◽  
Chip Thickness ◽  
Management Approach ◽  
High Flux ◽  
Thermo Electric ◽  
Wide Range ◽  
On Chip

Growing interest in germanium solid-state devices is raising concern over the effects of on-chip, micro-scaled, high flux hot spot on the reliability and performance of germanium chips. Current thermal management technology offers few choices for such on-chip hot spot remediation. However, the good thermo-electric properties of single crystal germanium support the development of a novel thermal management approach, relying on thermoelectric self-cooling by an electric current flowing in a thin planar layer on the back of the germanium chip. Use of metal-on-germanium fabrication techniques can yield a very low thermal contact resistance at the micro cooler/chip interface and the current flow can transfer the energy absorbed from a hot spot to the edge of the chip, thus substantially reducing the detrimental effect of thermoelectric heating on the temperature of the active circuitry. In this paper three-dimensional thermo-electric simulations are used to investigate the self-cooling of hot spots on a germanium chip for a wide range of input current, doping concentration, hot spot heat flux, micro cooler size, and germanium chip thickness. Results suggest that localized thermoelectric self-cooling on the germanium chip can significantly reduce the temperature rise resulting from micro-scaled high-flux hot spots.

Effect of Thermal Contact Resistance on Optimum Mini-Contact TEC Cooling of On-Chip Hot Spots

2009 ◽  
Author(s):  
Viatcheslav Litvinovitch ◽  
Avram Bar-Cohen
Keyword(s):  
Contact Resistance ◽  
Thermal Management ◽  
Hot Spots ◽  
High Performance ◽  
Thermal Contact Resistance ◽  
Hot Spot ◽  
Thermal Contact ◽  
Heat Fluxes ◽  
Thermoelectric Coolers ◽  
On Chip

Shrinking feature size and increasing transistor density, combined with the high performance demanded from next-generation microprocessors and other electronic components, have lead to the emergence of severe on-chip “hot spots,” with heat fluxes approaching — and at times exceeding — 1 kW/cm2. The cost-effective thermal management of such chips requires the introduction and refinement of novel cooling techniques. Mini-contact enhanced, miniaturized thermoelectric coolers (TECs) have been shown to be a viable approach for the remediation of on-chip hot spots, but their performance is constrained by the thermal resistance introduced by the attachment of this thermal management device. This paper uses a detailed finite-element package-level model to examine the parasitic effects of the thermal contact resistance (at the interfaces of the mini-contact and TEC) on the cooling efficacy of this thermal solution. Particular attention is devoted to the deleterious effect of contact resistance on the thermoelectric leg height and the mini-contact size required to achieve the greatest hot spot temperature reduction on the chip. Data from experiments with TECs (with a leg height of 130 μm) combined with several sizes of mini-contact pads, are used to validate the modeling approach and the overall conclusions.

Thermoelectric Micro-Cooler for Hot-Spot Thermal Management

2005 ◽  
Author(s):  
Peng Wang ◽  
Avram Bar-Cohen ◽  
Bao Yang ◽  
Gary L. Solbrekken ◽  
Yan Zhang ◽  
...  
Keyword(s):  
Solid State ◽  
Thermal Management ◽  
Hot Spots ◽  
Hot Spot ◽  
Electrical Contact ◽  
Chip Thickness ◽  
Great Promise ◽  
High Heat Flux ◽  
On Chip ◽  
Spot Temperature

Driven by shrinking feature sizes, microprocessor “hot-spots” — with their associated high heat flux and sharp temperature gradients — have emerged as the primary “driver” for on-chip thermal management of today’s IC technology. Solid state thermoelectric micro-coolers offer great promise for reducing the severity of on-chip “hot-spots”, but the theoretical cooling potential of these devices, fabricated on the back of the silicon die in an IC package, has yet to be determined. The results of a three-dimensional electro-thermal finite-element modeling study of such a micro-cooler are presented. Attention is focused on the hot-spot temperature reductions associated with variations in micro-cooler geometry, chip thickness, and chip doping concentration, along with the parasitic Joule heating effects from the electrical contact resistance and current flow through the silicon. The modeling results help to define the optimum solid-state cooling configuration and reveal that, for the conditions examined, nearly 80% of the hot-spot temperature rise of 2.5°C can be removed from a 70μm × 70μm, 680W/cm2 hot-spot on a 50μm thick silicon die with a single micro-cooler.

Analytical Modeling of On-Chip Hotspot Cooling Using Silicon Thermoelectric Microcoolers

2006 ◽  
Author(s):  
Peng Wang ◽  
Avram Bar-Cohen ◽  
Bao Yang
Keyword(s):  
Thermal Management ◽  
Joule Heating ◽  
Thermal Model ◽  
Analytical Modeling ◽  
Three Dimensional ◽  
Chip Thickness ◽  
The Novel ◽  
Conventional Cooling ◽  
On Chip ◽  
Analytical Thermal Model

Thermal management of microprocessors has become an increasing challenge in recent years because of localized high flux hotspots which can not be effectively removed by conventional cooling techniques. This paper describes the novel use of the silicon chip itself as thermoelectric microcooler to suppress the hotspot temperature. A three-dimensional analytical thermal model of the silicon chip, including localized silicon thermoelectric cooling, thermoelectric heating, Joule heating, hotspot heating, background heating, and conductive/convective cooling on the back of the silicon chip, is developed and used to predict the on-chip hotspot cooling performance. The effects of chip thickness, microcooler size, doping concentration and parasitic Joule heating from the electric contact resistance on hotspot cooling are investigated in details.

Thermal Management of On-Chip Hot Spot

2012 ◽  
Vol 134 (5) ◽  
Author(s):  
Avram Bar-Cohen ◽  
Peng Wang
Keyword(s):  
Heat Flux ◽  
Thermal Management ◽  
Hot Spots ◽  
Hot Spot ◽  
High Heat ◽  
High Heat Flux ◽  
Switching Speed ◽  
Two Phase ◽  
Advantages And Disadvantages ◽  
On Chip

The rapid emergence of nanoelectronics, with the consequent rise in transistor density and switching speed, has led to a steep increase in microprocessor chip heat flux and growing concern over the emergence of on-chip hot spots. The application of on-chip high flux cooling techniques is today a primary driver for innovation in the electronics industry. In this paper, the physical phenomena underpinning the most promising on-chip thermal management approaches for hot spot remediation, along with basic modeling equations and typical results are described. Attention is devoted to thermoelectric micro-coolers and two-phase microgap coolers. The advantages and disadvantages of these on-chip cooling solutions for high heat flux hot spots are evaluated and compared.

Investigation of On-Chip Hot Spot Cooling Using Microchannel Heat Sink

2013 ◽  
Vol 455 ◽  
pp. 466-469
Author(s):  
Yun Chuan Wu ◽  
Shang Long Xu ◽  
Chao Wang
Keyword(s):  
Heat Flux ◽  
Heat Sink ◽  
Hot Spots ◽  
Hot Spot ◽  
High Heat ◽  
High Heat Flux ◽  
Microchannel Heat Sink ◽  
Three Dimensional Model ◽  
Spot Cooling ◽  
On Chip

With the increase of performance demands, the nonuniformity of on-chip power dissipation becomes greater, causing localized high heat flux hot spots that can degrade the processor performance and reliability. In this paper, a three-dimensional model of the copper microchannel heat sink, with hot spot heating and background heating on the back, was developed and used for numerical simulation to predict the hot spot cooling performance. The hot spot is cooled by localized cross channels. The pressure drop, thermal resistance and effects of hot spot heat flux and fluid flow velocity on the cooling of on-chip hot spots, are investigated in detail.

Analysis of Thermal Properties of Power Multifinger HEMT Devices

2018 ◽  
Author(s):  
Aleš Chvála ◽  
Robert Szobolovszký ◽  
Jaroslav Kováč ◽  
Martin Florovič ◽  
Juraj Marek ◽  
...  
Keyword(s):  
Temperature Distribution ◽  
Thermal Management ◽  
High Electron Mobility Transistor ◽  
Structure Design ◽  
High Electron ◽  
Design And Optimization ◽  
Chip Temperature ◽  
Materials Used ◽  
On Chip ◽  
Measurement Approach

In this paper, several methods suitable for real time on-chip temperature measurements of power AlGaN/GaN based high-electron mobility transistor (HEMT) grown on SiC substrate are presented. The measurement of temperature distribution on HEMT surface using Raman spectroscopy is presented. We have deployed a temperature measurement approach utilizing electrical I-V characteristics of the neighboring Schottky diode under different dissipated power of the transistor heat source. These methods are verified by measurements with micro thermistors. The results show that these methods have a potential for HEMT analysis in thermal management. The features and limitations of the proposed methods are discussed. The thermal parameters of materials used in the device are extracted from temperature distribution in the structure with the support of 3-D device thermal simulation. The thermal analysis of the multifinger power HEMT is performed. The effects of the structure design and fabrication processes from semiconductor layers, metallization, and packaging up to cooling solutions are investigated. The analysis of thermal behavior can help during design and optimization of power HEMT.

Silicon Hot Spot Remediation With a Germanium Self Cooling Layer

2011 ◽  
Author(s):  
Horacio Nochetto ◽  
Peng Wang ◽  
Avram Bar-Cohen
Keyword(s):  
Hot Spots ◽  
Hot Spot ◽  
Silicon Layer ◽  
Great Promise ◽  
Applied Current ◽  
Chip Cooling ◽  
Primary Driver ◽  
Germanium Layer ◽  
On Chip ◽  
Spot Temperature

Driven by shrinking feature sizes, microprocessor hot spots have emerged as the primary driver for on-chip cooling of today’s IC technologies. Current thermal management technologies offer few choices for such on-chip hot spot remediation. A solid state germanium self-cooling layer, fabricated on top of the silicon chip, is proposed and demonstrated to have great promise for reducing the severity of on-chip hot spots. 3D thermo-electrical coupled simulations are used to investigate the effectiveness of a bi-layer device containing a germanium self-cooling layer above an electrically insulated silicon layer. The parametric variables of applied current, cooler size, silicon percentage, and total die thickness are sequentially optimized for the lowest hot spot temperature compared to a non-self-cooled silicon chip. Results suggest that the localized self-cooling of the germanium layer coupled with the higher thermal conductivity of the silicon chip can significantly reduce the temperature rise resulting from a micro-scaled hot spot.

Array of Thermoelectric Coolers for On-Chip Thermal Management

2012 ◽  
Vol 134 (2) ◽  
Author(s):  
Owen Sullivan ◽  
Man Prakash Gupta ◽  
Saibal Mukhopadhyay ◽  
Satish Kumar
Keyword(s):  
Steady State ◽  
Current Pulse ◽  
Hot Spots ◽  
Hot Spot ◽  
High Amplitude ◽  
Peak Temperature ◽  
Thermoelectric Coolers ◽  
Electronic Package ◽  
Current Pulses ◽  
On Chip

Site-specific on-demand cooling of hot spots in microprocessors can reduce peak temperature and achieve a more uniform thermal profile on chip, thereby improve chip performance and increase the processor’s life time. An array of thermoelectric coolers (TECs) integrated inside an electronic package has the potential to provide such efficient cooling of hot spots on chip. This paper analyzes the potential of using multiple TECs for hot spot cooling to obtain favorable thermal profile on chip in an energy efficient way. Our computational analysis of an electronic package with multiple TECs shows a strong conductive coupling among active TECs during steady-state operation. Transient operation of TECs is capable of driving cold-side temperatures below steady-state values. Our analysis on TEC arrays using current pulses shows that the effect of TEC coupling on transient cooling is weak. Various pulse profiles have been studied to illustrate the effect of shape of current pulse on the operation of TECs considering crucial parameters such as total energy consumed in TECs peak temperature on the chip, temperature overshoot at the hot spot and settling time during pulsed cooling of hot spots. The square root pulse profile is found to be the most effective with maximum cooling and at half the energy expenditure in comparison to a constant current pulse. We analyze the operation of multiple TECs for cooling spatiotemporally varying hot spots. The analysis shows that the transient cooling using high amplitude current pulses is beneficial for short term infrequent hot spots, but high amplitude current pulse cannot be used for very frequent or long lasting hot spots.

Temperature Sensor Allocation Strategy and Full Thermal Reconstruction for Microprocessors

2013 ◽  
Vol 380-384 ◽  
pp. 2986-2989
Author(s):  
Xin Li ◽  
Meng Tian Rong
Keyword(s):  
Thermal Management ◽  
Thermal Gradient ◽  
Gradient Analysis ◽  
Hot Spot ◽  
Temperature Sensors ◽  
Thermal Sensors ◽  
Dynamic Thermal Management ◽  
Effective Strategies ◽  
Management Techniques ◽  
On Chip

On-chip thermal sensors are employed by dynamic thermal management techniques to measure runtime thermal behavior of microprocessors so as to prevent the on-set of high temperatures. The allocation and the placement of thermal sensors directly impact the effectiveness of the dynamic thermal management mechanisms. In this paper, we propose systematic and effective strategies for determining the optimal locations for temperature sensors based on thermal gradient analysis to provide the trade-off between hot spot estimation and full thermal reconstruction. Experimental results indicate the superiority of our techniques and confirm that our proposed methods are able to create a sensor distribution for a given microprocessor architecture.

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