Surface activated bonding of copper through silicon vias and gold stud bumps at room temperature

2011 ◽  
Vol 29 (2) ◽  
pp. 021007 ◽  
Author(s):  
M. M. R. Howlader ◽  
F. Zhang ◽  
M. J. Deen ◽  
T. Suga ◽  
A. Yamauchi
Keyword(s):  
Room Temperature ◽  
Through Silicon Vias ◽  
Silicon Vias

The Effect of Thermal Prestress on the Deformation of Micromirror Chip Embedded with Through-Silicon Vias

2011 ◽  
Vol 462-463 ◽  
pp. 563-568 ◽  
Author(s):  
Meng Kao Yeh ◽  
Chun Lin Lu
Keyword(s):  
Stress Distribution ◽  
Room Temperature ◽  
Thermal Loading ◽  
Heat Transfer Analysis ◽  
Processing Temperature ◽  
Temperature Decrease ◽  
Analysis Method ◽  
The Finite Element Method ◽  
Through Silicon Vias ◽  
Silicon Vias

The thermal expansion mismatch problem for a chip due to temperature decrease from processing temperature to room temperature may cause residual stress inside the chip structure. The thermal prestress accumulated and may affect the chip reliability when the chip was subjected to the thermal loading again. In this paper, the effect of thermal prestress on the micromirror chip embedded with copper through-silicon vias (TSVs) was investigated by the finite element method. In analysis, the micromirror chip embedded with TSVs was analyzed first under thermal loading which resulted from temperature decrease between the stress free processing temperature and room temperature. This process produced a thermal prestress in the micromirror chip. The chip was then subjected to a heat source at the bottom while in operation and the heat transfer analysis was used to simulate this situation. Finally, the thermal stress analysis was carried out to obtain the deformation and the stress distribution in the chip. The results show that the thermal prestress had strong effect on the chip reliability and should be reduced as much as possible. This paper proposed a three steps analysis method to obtain the deformation and the stress distribution in the chip, in which the effect of thermal prestress on the chip reliability was evaluated effectively.

Failure and Stress Analysis of Cu TSVs Using GHz-Scanning Acoustic Microscopy and Scanning Infrared Polariscopy

2015 ◽  
Author(s):  
Ingrid De Wolf ◽  
Ahmad Khaled ◽  
Martin Herms ◽  
Matthias Wagner ◽  
Tatjana Djuric ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Stress Analysis ◽  
Rayleigh Waves ◽  
Acoustic Microscopy ◽  
Scanning Acoustic Microscopy ◽  
Through Silicon Vias ◽  
Stress Anisotropy ◽  
Silicon Vias ◽  
Ic Technology ◽  
Detection Of Defects

Abstract This paper discusses the application of two different techniques for failure analysis of Cu through-silicon vias (TSVs), used in 3D stacked-IC technology. The first technique is GHz Scanning Acoustic Microscopy (GHz- SAM), which not only allows detection of defects like voids, cracks and delamination, but also the visualization of Rayleigh waves. GHz-SAM can provide information on voids, delamination and possibly stress near the TSVs. The second is a reflection-based photoelastic technique (SIREX), which is shown to be very sensitive to stress anisotropy in the Si near TSVs and as such also to any defect affecting this stress, such as delamination and large voids.

scholarly journals Resistive Programmable Through-Silicon Vias for Reconfigurable 3-D Fabrics

2012 ◽  
Vol 11 (1) ◽  
pp. 8-11 ◽  
Author(s):  
Davide Sacchetto ◽  
Michael Zervas ◽  
Yuksel Temiz ◽  
Giovanni De Micheli ◽  
Yusuf Leblebici
Keyword(s):  
Through Silicon Vias ◽  
Silicon Vias
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