Design and implementation of a high-performance readout circuit for uncooled infrared detector

2015 ◽  
Author(s):  
Honghui Yuan ◽  
Shijun Chen ◽  
Houming Zhai ◽  
Yongping Chen
Keyword(s):  
High Performance ◽  
Infrared Detector ◽  
Readout Circuit ◽  
Design And Implementation

scholarly journals Robust trap effect in transition metal dichalcogenides for advanced multifunctional devices

2019 ◽  
Vol 10 (1) ◽  
Author(s):  
Lei Yin ◽  
Peng He ◽  
Ruiqing Cheng ◽  
Feng Wang ◽  
Fengmei Wang ◽  
...  
Keyword(s):  
Transition Metal ◽  
High Performance ◽  
Infrared Detector ◽  
Transition Metal Dichalcogenides ◽  
Two Dimensional ◽  
Electric Transport ◽  
Defect Engineering ◽  
Fast Switching ◽  
Metal Dichalcogenides ◽  
Poor Stability

Abstract Defects play a crucial role in determining electric transport properties of two-dimensional transition metal dichalcogenides. In particular, defect-induced deep traps have been demonstrated to possess the ability to capture carriers. However, due to their poor stability and controllability, most studies focus on eliminating this trap effect, and little consideration was devoted to the applications of their inherent capabilities on electronics. Here, we report the realization of robust trap effect, which can capture carriers and store them steadily, in two-dimensional MoS2xSe2(1-x) via synergistic effect of sulphur vacancies and isoelectronic selenium atoms. As a result, infrared detection with very high photoresponsivity (2.4 × 105 A W−1) and photoswitching ratio (~108), as well as nonvolatile infrared memory with high program/erase ratio (~108) and fast switching time, are achieved just based on an individual flake. This demonstration of defect engineering opens up an avenue for achieving high-performance infrared detector and memory.

scholarly journals Design and implementation of CNTFET based ternary 1x1 memories

2019 ◽  
Vol 8 (3) ◽  
pp. 175 ◽  
Author(s):  
S.Tamil Selvan ◽  
M. Sundararajan
Keyword(s):  
High Performance ◽  
Data Access ◽  
Cmos Technology ◽  
Access Time ◽  
The Novel ◽  
Design And Implementation ◽  
Technology Process ◽  
Sram Cell ◽  
And Performance ◽  
Power Application

In this paper presented Design and implementation of CNTFET based Ternary 1x1 RAM memories high-performance digital circuits. CNTFET Ternary 1x1 SRAM memories is implement using 32nm technology process. The CNTFET decresase the diameter and performance matrics like delay,power and power delay, The CNTFET Ternary 6T SRAM cell consists of two cross coupled Ternary inverters one is READ and another WRITE operations of the Ternary 6T SRAM cell are performed with the Tritline using HSPICE and Tanner tools in this tool is performed high accuracy. The novel based work can be used for Low Power Application and Access time is less of compared to the conventional CMOS Technology. The CNTFET Ternary 6T SRAM array module (1X1) in 32nm technology consumes only 0.412mW power and data access time is about 5.23ns.

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